Microchip Technology TDGL019 Data Sheet

PIC32MX1XX/2XX

DS600011

68F-

page 44

2011-

2014 Microchip T

echnolo

gy Inc.

TABLE 4-3:

TIMER1-TIMER5 REGISTER MAP

irtual Address

(BF80_#

)

Regis

ter

Name

(1)

Bit Range

Bits

All

set

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

0600 T1CON

31:16

—

0000

15:0

—

SIDL

TWDIS

TWIP

—

TGATE

—

TCKPS<1:0>

—

TSYNC

TCS

—

0000

0610 TMR1

31:16

—

0000

15:0

TMR1<15:0>

0000

0620

PR1

31:16

—

0000

15:0

PR1<15:0>

FFFF

0800 T2CON

31:16

—

0000

15:0

—

SIDL

—

TGATE

TCKPS<2:0>

T32

—

TCS

—

0000

0810 TMR2

31:16

—

0000

15:0

TMR2<15:0>

0000

0820

PR2

31:16

—

0000

15:0

PR2<15:0>

FFFF

0A00 T3CON

31:16

—

0000

15:0

—

SIDL

—

TGATE

TCKPS<2:0>

—

TCS

—

0000

0A10 TMR3

31:16

—

0000

15:0

TMR3<15:0>

0000

0A20

PR3

31:16

—

0000

15:0

PR3<15:0>

FFFF

0C00 T4CON

31:16

—

0000

15:0

—

SIDL

—

TGATE

TCKPS<2:0>

T32

—

TCS

—

0000

0C10 TMR4

31:16

—

0000

15:0

TMR4<15:0>

0000

0C20

PR4

31:16

—

0000

15:0

PR4<15:0>

FFFF

0E00 T5CON

31:16

—

0000

15:0

—

SIDL

—

TGATE

TCKPS<2:0>

—

TCS

—

0000

0E10 TMR5

31:16

—

0000

15:0

TMR5<15:0>

0000

0E20

PR5

31:16

—

0000

15:0

PR5<15:0>

FFFF

Legend:

= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1:

All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See

Section 11.2 “CLR, SET and INV Registers”

for

more information.