Microchip Technology TDGL019 Data Sheet

PIC32MX1XX/2XX

DS600011

68F-

page 46

2011-

2014 Microchip T

echnolo

gy Inc.

TABLE 4-5:

OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAP

irtual Address

(BF80_#

)

Regis

ter

Name

(1)

Bit Range

Bits

All

set

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

3000 OC1CON

31:16

—

0000

15:0

—

SIDL

—

OC32

OCFLT

OCTSEL

OCM<2:0>

0000

3010

OC1R

31:16

OC1R<31:0>

xxxx

15:0

xxxx

3020 OC1RS

31:16

OC1RS<31:0>

xxxx

15:0

xxxx

3200 OC2CON

31:16

—

0000

15:0

—

SIDL

—

OC32

OCFLT

OCTSEL

OCM<2:0>

0000

3210

OC2R

31:16

OC2R<31:0>

xxxx

15:0

xxxx

3220 OC2RS

31:16

OC2RS<31:0>

xxxx

15:0

xxxx

3400 OC3CON

31:16

—

0000

15:0

—

SIDL

—

OC32

OCFLT

OCTSEL

OCM<2:0>

0000

3410

OC3R

31:16

OC3R<31:0>

xxxx

15:0

xxxx

3420 OC3RS

31:16

15:0

OC3RS<31:0>

xxxx

3600 OC4CON

31:16

—

0000

15:0

—

SIDL

—

OC32

OCFLT

OCTSEL

OCM<2:0>

0000

3610

OC4R

31:16

OC4R<31:0>

xxxx

15:0

xxxx

3620 OC4RS

31:16

15:0

OC4RS<31:0>

xxxx

3800 OC5CON

31:16

—

0000

15:0

—

SIDL

—

OC32

OCFLT

OCTSEL

OCM<2:0>

0000

3810

OC5R

31:16

OC5R<31:0>

xxxx

15:0

xxxx

3820 OC5RS

31:16

OC5RS<31:0>

xxxx

15:0

xxxx

Legend:

= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1:

All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See

Section 11.2 “CLR, SET and INV Registers”

for

more information.