Microchip Technology MA330028 Data Sheet
2011-2013 Microchip Technology Inc.
DS70000657H-page 111
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
4.4.4
SOFTWARE STACK
The W15 register serves as a dedicated Software
Stack Pointer (SSP) and is automatically modified by
exception processing, subroutine calls and returns;
however, W15 can be referenced by any instruction in
the same manner as all other W registers. This
simplifies reading, writing and manipulating of the
Stack Pointer (for example, creating stack frames).
Stack Pointer (SSP) and is automatically modified by
exception processing, subroutine calls and returns;
however, W15 can be referenced by any instruction in
the same manner as all other W registers. This
simplifies reading, writing and manipulating of the
Stack Pointer (for example, creating stack frames).
W15 is initialized to 0x1000 during all Resets. This
address ensures that the SSP points to valid RAM in all
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X devices, and permits
stack availability for non-maskable trap exceptions.
These can occur before the SSP is initialized by the user
software. You can reprogram the SSP during
initialization to any location within Data Space.
The Software Stack Pointer always points to the first
available free word and fills the software stack
working from lower toward higher addresses.
address ensures that the SSP points to valid RAM in all
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X devices, and permits
stack availability for non-maskable trap exceptions.
These can occur before the SSP is initialized by the user
software. You can reprogram the SSP during
initialization to any location within Data Space.
The Software Stack Pointer always points to the first
available free word and fills the software stack
working from lower toward higher addresses.
illustrates how it pre-decrements for a
stack pop (read) and post-increments for a stack push
(writes).
When the PC is pushed onto the stack, PC<15:0> are
pushed onto the first available stack word, then
PC<22:16> are pushed into the second available stack
location. For a PC push during any CALL instruction,
the MSB of the PC is zero-extended before the push,
as shown in
(writes).
When the PC is pushed onto the stack, PC<15:0> are
pushed onto the first available stack word, then
PC<22:16> are pushed into the second available stack
location. For a PC push during any CALL instruction,
the MSB of the PC is zero-extended before the push,
as shown in
. During exception processing,
the MSB of the PC is concatenated with the lower 8 bits
of the CPU STATUS Register, SR. This allows the
contents of SRL to be preserved automatically during
interrupt processing.
of the CPU STATUS Register, SR. This allows the
contents of SRL to be preserved automatically during
interrupt processing.
FIGURE 4-19:
CALL
STACK FRAME
Note:
To protect against misaligned stack
accesses, W15<0> is fixed to ‘0’ by the
hardware.
accesses, W15<0> is fixed to ‘0’ by the
hardware.
Note 1:
To maintain system Stack Pointer (W15)
coherency, W15 is never subject to
(EDS) paging, and is therefore restricted
to an address range of 0x0000 to
0xFFFF. The same applies to the W14
when used as a Stack Frame Pointer
(SFA = 1).
coherency, W15 is never subject to
(EDS) paging, and is therefore restricted
to an address range of 0x0000 to
0xFFFF. The same applies to the W14
when used as a Stack Frame Pointer
(SFA = 1).
2:
As the stack can be placed in, and can
access X and Y spaces, care must be
taken regarding its use, particularly with
regard to local automatic variables in a C
development environment
access X and Y spaces, care must be
taken regarding its use, particularly with
regard to local automatic variables in a C
development environment
<Free Word>
PC<15:0>
b‘000000000’
0
15
W15 (before CALL)
W15 (after CALL)
S
ta
ck G
ro
w
s
To
wa
rd
Hig
her Ad
dre
ss
0x0000
PC<22:16>
CALL SUBR