Microchip Technology MA330028 Data Sheet

 2011-2013 Microchip Technology Inc.

DS70000657H-page 131

Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this 

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and additional information.

7.3.1

KEY RESOURCES

• “Interrupts” (DS70600) in the “dsPIC33/PIC24 

• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference 

 Sections

• Development Tools

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X devices implement the
following registers for the interrupt controller: 
• INTCON1 
• INTCON2 
• INTCON3
• INTCON4
• INTTREG

7.4.1

INTCON1 THROUGH INTCON4

Global interrupt control functions are controlled from
INTCON1, INTCON2, INTCON3 and INTCON4.
INTCON1 contains the Interrupt Nesting Disable bit
(NSTDIS), as well as the control and status flags for the
processor trap sources. 
The INTCON2 register controls external interrupt
request signal behavior and also contains the Global
Interrupt Enable bit (GIE).
INTCON3 contains the status flags for the DMA and DO
stack overflow status trap sources.
The INTCON4 register contains the software
generated hard trap status bit (SGHT).

7.4.2

IFSx

The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.

7.4.3

IECx

The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.

7.4.4

IPCx

The IPCx registers are used to set the Interrupt Priority
Level (IPL) for each source of interrupt. Each user
interrupt source can be assigned to one of eight priority
levels. 

7.4.5

INTTREG

The INTTREG register contains the associated
interrupt vector number and the new CPU Interrupt
Priority Level, which are latched into the Vector
Number bits (VECNUM<7:0>) and Interrupt Priority
Level bits (ILR<3:0>) fields in the INTTREG register.
The new Interrupt Priority Level is the priority of the
pending interrupt. 
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence as they are
listed in 

. For example, the INT0 (External

Interrupt 0) is shown as having Vector Number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit in IEC0<0> and the INT0IP
bits in the first position of IPC0 (IPC0<2:0>). 

7.4.6

STATUS/CONTROL REGISTERS

Although these registers are not specifically part of the
interrupt control hardware, two of the CPU Control
registers contain bits that control interrupt functionality.
For more information on these registers refer to “CPU”
(DS70359) in the “dsPIC33/PIC24 Family Reference
Manual”

.

• The CPU STATUS Register, SR, contains the 

IPL<2:0> bits (SR<7:5>). These bits indicate the 
current CPU Interrupt Priority Level. The user 
software can change the current CPU Interrupt 
Priority Level by writing to the IPLx bits. 

• The CORCON register contains the IPL3 bit 

which, together with IPL<2:0>, also indicates the 
current CPU priority level. IPL3 is a read-only bit 
so that trap events cannot be masked by the user 
software.

All Interrupt registers are described in 

through 

 in the following pages.

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