Microchip Technology MA330028 Data Sheet
2011-2013 Microchip Technology Inc.
DS70000657H-page 171
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 10-6:
PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
U-0
U-0
U-0
—
—
—
DMA0MD
)
PTGMD
—
—
—
DMA1MD
)
DMA2MD
)
DMA3MD
)
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-5
Unimplemented:
Read as ‘0’
bit 4
DMA0MD:
DMA0 Module Disable bit
(
)
1
= DMA0 module is disabled
0
= DMA0 module is enabled
DMA1MD:
DMA1 Module Disable bit
(
)
1
= DMA1 module is disabled
0
= DMA1 module is enabled
DMA2MD:
DMA2 Module Disable bit
(
)
1
= DMA2 module is disabled
0
= DMA2 module is enabled
DMA3MD:
DMA3 Module Disable bit
(
)
1
= DMA3 module is disabled
0
= DMA3 module is enabled
bit 3
PTGMD:
PTG Module Disable bit
1
= PTG module is disabled
0
= PTG module is enabled
bit 2-0
Unimplemented:
Read as ‘0’
Note 1:
This single bit enables and disables all four DMA channels.