Microchip Technology MA330028 Data Sheet

 2011-2013 Microchip Technology Inc.

DS70000657H-page 225

The dsPIC33EPXXXMC20X/50X and
PIC24EPXXXMC20X devices support a dedicated
Pulse-Width Modulation (PWM) module with up to
6 outputs.
The high-speed PWMx module consists of the
following major features:
• Three PWM generators
• Two PWM outputs per PWM generator
• Individual period and duty cycle for each PWM pair
• Duty cycle, dead time, phase shift and frequency 

resolution of T

CY

/2 (7.14 ns at F

CY

 = 70MHz)

• Independent Fault and current-limit inputs for 

six PWM outputs

• Redundant output
• Center-Aligned PWM mode
• Output override control
• Chop mode (also known as Gated mode)
• Special Event Trigger
• Prescaler for input clock
• PWMxL and PWMxH output pin swapping
• Independent PWM frequency, duty cycle and 

phase-shift changes for each PWM generator

• Dead-time compensation
• Enhanced Leading-Edge Blanking (LEB) 

functionality

• Frequency resolution enhancement
• PWM capture functionality

The high-speed PWMx module contains up to three
PWM generators. Each PWM generator provides two
PWM outputs: PWMxH and PWMxL

.

 The master time

base generator provides a synchronous signal as a
common time base to synchronize the various PWM
outputs.

 

The individual PWM outputs are available on

the output pins of the device. The input Fault signals
and current-limit signals, when enabled, can monitor
and protect the system by placing the PWM outputs
into a known “safe” state.
Each PWMx can generate a trigger to the ADC module
to sample the analog signal at a specific instance
during the PWM period. In addition, the high-speed
PWMx module also generates a Special Event Trigger
to the ADC module based on either of the two master
time bases. 
The high-speed PWMx module can synchronize itself
with an external signal or can act as a synchronizing
source to any external device. The SYNCI1 input pin
that utilizes PPS, can synchronize the high-speed
PWMx module with an external signal. The SYNCO1
pin is an output pin that provides a synchronous signal
to an external device.

 illustrates an architectural overview of the

high-speed PWMx module and its interconnection with
the CPU and other peripherals.

The PWMx module incorporates multiple external Fault
inputs to include FLT1 and FLT2 which are re-
mappable using the PPS feature, FLT3 and FLT4 which
are available only on the larger 44-pin and 64-pin
packages, and FLT32 which has been implemented
with Class B safety features, and is available on a
fixed pin on all dsPIC33EPXXXMC20X/50X and
PIC24EPXXXMC20X devices. 
These Faults provide a safe and reliable way to safely
shut down the PWM outputs when the Fault input is
asserted. 

16.1.1

PWM FAULTS AT RESET 

During any Reset event, the PWMx module maintains
ownership of the Class B Fault, FLT32. At Reset, this
Fault is enabled in Latched mode to ensure the fail-safe
power-up of the application. The application software
must clear the PWM Fault before enabling the high-
speed motor control PWMx module. To clear the Fault
condition, the FLT32 pin must first be pulled low
externally or the internal pull-down resistor in the
CNPDx register can be enabled.

This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to “High-Speed PWM” (DS70645)
in the “dsPIC33/PIC24 Family Reference
Manual

”, which is available from the

www.microchip.com

).

Some registers and associated bits
described in this section may not be
available on all devices. Refer to

 in

this data sheet for device-specific register
and bit information.

In Edge-Aligned PWM mode, the duty
cycle, dead time, phase shift and
frequency resolution are 8.32 ns.

The Fault mode may be changed using
the FLTMOD<1:0> bits (FCLCON<1:0>),
regardless of the state of FLT32.