Microchip Technology MA330028 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 228
2011-2013 Microchip Technology Inc.
FIGURE 16-2:
HIGH-SPEED PWMx MODULE REGISTER INTERCONNECTION DIAGRAM
MUX
PTMRx
PDCx
PWMCONx,
PTCON, PTCON2
IOCONx
DTRx
PWMxL
PWMxH
FLTx
PWM1L
PWM1H
FCLCONx
MDC
PHASEx
LEBCONx,
ALTDTRx
User Override Logic
Current-Limit
PWM Output Mode
Control Logic
Logic
Pin
Control
Logic
Fault and
Current-Limit
Logic
PWM Generator 1
FLTx
PWM Generator 2 and PWM Generator 3
Interrupt
Logic
(1)
Module Control and Timing
Master Duty Cycle Register
S
yn
chr
on
iz
at
io
n
S
yn
chr
on
iz
at
io
n
Ma
st
er
P
e
rio
d
Ma
st
e
r P
er
iod
M
ast
er
Duty
C
ycle
M
ast
er
Duty
C
ycle
SYNCI1
SYNCO1
SEVTCMP
Comparator
Special Event Trigger
Special Event
Postscaler
PTPER
PMTMR
Primary Master Time Base
Master Time Base Counter
Special Event Compare Trigger
Comparator
Clock
Prescaler
Comparator
Dead-Time
Fault Override Logic
Override Logic
DTCMPx
DTCMP1
F
OSC
PWMKEY
IOCONx and FCLCONx Unlock Register
AUXCONx
LEBDLYx
PTG Trigger
Input
PTG Trigger Input
PTG Trigger Input
TRGCONx
PWMCAPx
ADC Trigger
Comparator
TRIGx
16-
B
it Data B
u
s
Note
1:
The PWM interrupts are generated by logically ORing the FLTSTAT, CLSTAT and TRGSTAT status bits for the
given PWM generator. Refer to the “dsPIC33/PIC24 Family Reference Manual”, “High-Speed PWM”
(DS70645) for more information.
given PWM generator. Refer to the “dsPIC33/PIC24 Family Reference Manual”, “High-Speed PWM”
(DS70645) for more information.