Microchip Technology MA330028 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 240
2011-2013 Microchip Technology Inc.
REGISTER 16-13: IOCONx: PWMx I/O CONTROL REGISTER
(
)
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PENH
PENL
POLH
POLL
PMOD1
(
)
PMOD0
)
OVRENH
OVRENL
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OVRDAT1
OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
PENH:
PWMxH Output Pin Ownership bit
1
= PWMx module controls PWMxH pin
0
= GPIO module controls PWMxH pin
bit 14
PENL:
PWMxL Output Pin Ownership bit
1
= PWMx module controls PWMxL pin
0
= GPIO module controls PWMxL pin
bit 13
POLH:
PWMxH Output Pin Polarity bit
1
= PWMxH pin is active-low
0
= PWMxH pin is active-high
bit 12
POLL:
PWMxL Output Pin Polarity bit
1
= PWMxL pin is active-low
0
= PWMxL pin is active-high
bit 11-10
PMOD<1:0>:
PWMx # I/O Pin Mode bits
(
)
11
= Reserved; do not use
10
= PWMx I/O pin pair is in the Push-Pull Output mode
01
= PWMx I/O pin pair is in the Redundant Output mode
00
= PWMx I/O pin pair is in the Complementary Output mode
bit 9
OVRENH:
Override Enable for PWMxH Pin bit
1
= OVRDAT<1> controls output on PWMxH pin
0
= PWMx generator controls PWMxH pin
bit 8
OVRENL:
Override Enable for PWMxL Pin bit
1
= OVRDAT<0> controls output on PWMxL pin
0
= PWMx generator controls PWMxL pin
bit 7-6
OVRDAT<1:0>:
Data for PWMxH, PWMxL Pins if Override is Enabled bits
If OVERENH = 1, PWMxH is driven to the state specified by OVRDAT<1>.
If OVERENL = 1, PWMxL is driven to the state specified by OVRDAT<0>.
If OVERENL = 1, PWMxL is driven to the state specified by OVRDAT<0>.
bit 5-4
FLTDAT<1:0>:
Data for PWMxH and PWMxL Pins if FLTMOD is Enabled bits
If Fault is active, PWMxH is driven to the state specified by FLTDAT<1>.
If Fault is active, PWMxL is driven to the state specified by FLTDAT<0>.
If Fault is active, PWMxL is driven to the state specified by FLTDAT<0>.
bit 3-2
CLDAT<1:0>:
Data for PWMxH and PWMxL Pins if CLMOD is Enabled bits
If current-limit is active, PWMxH is driven to the state specified by CLDAT<1>.
If current-limit is active, PWMxL is driven to the state specified by CLDAT<0>.
If current-limit is active, PWMxL is driven to the state specified by CLDAT<0>.
Note 1:
These bits should not be changed after the PWMx module is enabled (PTEN = 1).
2:
If the PWMLOCK Configuration bit (FOSCSEL<6>) is a ‘1’, the IOCONx register can only be written after
the unlock sequence has been executed.
the unlock sequence has been executed.