Microchip Technology MA330028 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 256
2011-2013 Microchip Technology Inc.
REGISTER 17-3:
QEI1STAT: QEI1 STATUS REGISTER
U-0
U-0
HS, R/C-0
R/W-0
HS, R/C-0
R/W-0
HS, R/C-0
R/W-0
—
—
PCHEQIRQ
PCHEQIEN PCLEQIRQ
PCLEQIEN
POSOVIRQ
POSOVIEN
bit 15
bit 8
HS, R/C-0
R/W-0
HS, R/C-0
R/W-0
HS, R/C-0
R/W-0
HS, R/C-0
R/W-0
PCIIRQ
(
)
PCIIEN
VELOVIRQ
VELOVIEN
HOMIRQ
HOMIEN
IDXIRQ
IDXIEN
bit 7
bit 0
Legend:
HS = Hardware Settable bit
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented:
Read as ‘0’
bit 13
PCHEQIRQ:
Position Counter Greater Than or Equal Compare Status bit
1
= POS1CNT ≥ QEI1GEC
0
= POS1CNT < QEI1GEC
bit 12
PCHEQIEN:
Position Counter Greater Than or Equal Compare Interrupt Enable bit
1
= Interrupt is enabled
0
= Interrupt is disabled
bit 11
PCLEQIRQ:
Position Counter Less Than or Equal Compare Status bit
1
= POS1CNT ≤ QEI1LEC
0
= POS1CNT > QEI1LEC
bit 10
PCLEQIEN:
Position Counter Less Than or Equal Compare Interrupt Enable bit
1
= Interrupt is enabled
0
= Interrupt is disabled
bit 9
POSOVIRQ:
Position Counter Overflow Status bit
1
= Overflow has occurred
0
= No overflow has occurred
bit 8
POSOVIEN:
Position Counter Overflow Interrupt Enable bit
1
= Interrupt is enabled
0
= Interrupt is disabled
bit 7
PCIIRQ:
Position Counter (Homing) Initialization Process Complete Status bit
(
1
= POS1CNT was reinitialized
0
= POS1CNT was not reinitialized
bit 6
PCIIEN:
Position Counter (Homing) Initialization Process Complete interrupt Enable bit
1
= Interrupt is enabled
0
= Interrupt is disabled
bit 5
VELOVIRQ:
Velocity Counter Overflow Status bit
1
= Overflow has occurred
0
= No overflow has not occurred
bit 4
VELOVIEN:
Velocity Counter Overflow Interrupt Enable bit
1
= Interrupt is enabled
0
= Interrupt is disabled
bit 3
HOMIRQ:
Status Flag for Home Event Status bit
1
= Home event has occurred
0
= No Home event has occurred
Note 1:
This status bit is only applicable to PIMOD<2:0> modes, ‘011’ and ‘100’.