Microchip Technology MA330028 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 36
2011-2013 Microchip Technology Inc.
FIGURE 3-1:
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
CPU BLOCK DIAGRAM
CPU BLOCK DIAGRAM
Instruction
Decode and
Control
16
PCL
16
Program Counter
16-Bit ALU
24
24
24
24
X Data Bus
PCU
16
16
16
Divide
Support
Engine
(1)
DSP
R
O
M Latc
h
16
Y Data Bus
(1)
EA MUX
X RAGU
X WAGU
Y AGU
(1)
16
24
16
16
16
16
16
16
16
8
Interrupt
Controller
PSV and Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data Latch
Data Latch
Y Data
RAM
(1)
X Data
RAM
Address
Latch
Address
Latch
16
Data Latch
16
16
16
X Address Bus
Y
A
ddr
ess
B
u
s
24
Li
te
ra
l Da
ta
Program Memory
Address Latch
Power, Reset
and Oscillator
Control Signals
to Various Blocks
to Various Blocks
Ports
Peripheral
Modules
Note
1:
This feature is not available on PIC24EPXXXGP/MC20X devices.
Modules
PCH
IR
16 x 16
W Register Array