Microchip Technology MA330028 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 516
2011-2013 Microchip Technology Inc.
Revision H (August 2013)
This revision includes minor typographical and
formatting changes throughout the text.
Other major changes are referenced by their respective
section in
formatting changes throughout the text.
Other major changes are referenced by their respective
section in
TABLE A-6:
MAJOR SECTION UPDATES
Section Name
Update Description
• Adds Peripheral Pin Select (PPS) to allow Digital Function Remapping and Change
Notification Interrupts to Input/Output section
• Adds heading information to 64-Pin TQFP
• Corrects Reset values for ANSELE, TRISF, TRISC, ANSELC and TRISA
• Corrects address range from 0x2FFF to 0x7FFF
• Corrects DSRPAG and DSWPAG (now 3 hex digits)
• Changes Call Stack Frame from <15:1> to PC<15:0>
• Word length in
• Word length in
is changed to 50 words for clarity
•
Corrects descriptions of NVM registers
• Removes resistor from
• Removes incorrect information from ROI bit in
• Changes 31 user-selectable Trigger/Sync interrupts to 19 user-selectable Trigger/
Sync interrupts
• Corrects ICTSEL<12:10> bits (now ICTSEL<2:0>)
•
Corrects QCAPEN bit description
• Adds note to clarify that 100kbit/sec operation of I
2
C is not possible at high processor
speeds
• Clarifies
(changes CH123x to CH123Sx)
• Adds footnote to
(In order to operate with CVRSS=1, at least one of the
comparator modules must be enabled.
(In order to operate with CVRSS=1, at least one of the
comparator modules must be enabled)
• Adds footnote to
(COE is not available when OPMODE
(CMxCON<10>) = 1)
• Corrects the bit description for FNOSC<2:0>
• Corrects 512K part power-down currents based on test data
• Corrects WDT timing limits based on LPRC oscillator tolerance
• Corrects WDT timing limits based on LPRC oscillator tolerance
• Adds
(DC Characteristics: Idle Current (I
IDLE
)