Microchip Technology MA330028 Data Sheet
2011-2
013 M
ic
rochip
T
e
chnology
In
c.
DS70000657H
-page
79
dsPI
C3
3E
PXX
3E
PXX
XGP5
0X
, dsP
, dsP
IC
3
3
EPX
XXM
C
2
0
X
/5
0X
A
N
A
N
D
P
IC
IC
2
4
EPX
XXG
P/M
C
20
X
X
TABLE 4-12:
PWM REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
PTCON
0C00
PTEN
—
PTSIDL
SESTAT
SEIEN
EIPU
SYNCPOL SYNCOEN SYNCEN
SYNCSRC<2:0>
SEVTPS<3:0>
0000
PTCON2
0C02
—
—
—
—
—
—
—
—
—
—
—
—
—
PCLKDIV<2:0>
0000
PTPER
0C04
PTPER<15:0>
00F8
SEVTCMP
0C06
SEVTCMP<15:0>
0000
MDC
0C0A
MDC<15:0>
0000
CHOP
0C1A CHPCLKEN
—
—
—
—
—
CHOPCLK<9:0>
0000
PWMKEY
0C1E
PWMKEY<15:0>
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-13:
PWM GENERATOR 1 REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
PWMCON1 0C20
FLTSTAT
CLSTAT TRGSTAT FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTC<1:0>
DTCP
—
MTBS
CAM
XPRES
IUE
0000
IOCON1
0C22
PENH
PENL
POLH
POLL
PMOD<1:0>
OVRENH
OVRENL
OVRDAT<1:0>
FLTDAT<1:0>
CLDAT<1:0>
SWAP
OSYNC
C000
FCLCON1
0C24
—
CLSRC<4:0>
CLPOL
CLMOD
FLTSRC<4:0>
FLTPOL
FLTMOD<1:0>
0000
PDC1
0C26
PDC1<15:0>
FFF8
PHASE1
0C28
PHASE1<15:0>
0000
DTR1
0C2A
—
—
DTR1<13:0>
0000
ALTDTR1
0C2C
—
—
ALTDTR1<13:0>
0000
TRIG1
0C32
TRGCMP<15:0>
0000
TRGCON1
0C34
TRGDIV<3:0>
—
—
—
—
—
—
TRGSTRT<5:0>
0000
LEBCON1
0C3A
PHR
PHF
PLR
PLF
FLTLEBEN CLLEBEN
—
—
—
—
BCH
BCL
BPHH
BPHL
BPLH
BPLL
0000
LEBDLY1
0C3C
—
—
—
—
LEB<11:0>
0000
AUXCON1
0C3E
—
—
—
—
BLANKSEL<3:0>
—
—
CHOPSEL<3:0>
CHOPHEN CHOPLEN
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.