Microchip Technology MCP1631RD-MCC2 Data Sheet

DS41291G-page 200

 2006-2012 Microchip Technology Inc.

13.4.6

I

2

C™ MASTER MODE START 

CONDITION TIMING

To initiate a Start condition, the user sets the Start Con-
dition Enable bit SEN of the SSPCON2 register. If the
SDA and SCL pins are sampled high, the Baud Rate
Generator is reloaded with the contents of
SSPADD<6:0> and starts its count. If SCL and SDA are
both sampled high when the Baud Rate Generator
times out (T

BRG

), the SDA pin is driven low. The action

of the SDA being driven low, while SCL is high, is the
Start condition, and causes the S bit of the SSPSTAT
register to be set. Following this, the Baud Rate Gener-
ator is reloaded with the contents of SSPADD<6:0>
and resumes its count. When the Baud Rate Generator
times out (T

BRG

), the SEN bit of the SSPCON2 register

will be automatically cleared by hardware, the Baud
Rate Generator is suspended leaving the SDA line held
low and the Start condition is complete.      

13.4.6.1

WCOL Status Flag

If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).    

If, at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low, or if during the Start condition the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag, BCLIF, is
set, the Start condition is aborted, and the
I

2

C module is reset into its Idle state.

Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.

SDA

SCL

S

T

BRG

1st Bit

2nd Bit

T

BRG

SDA = 1, 

At completion of Start bit,

SCL = 1

Write to SSPBUF occurs here

T

BRG

hardware clears SEN bit

T

BRG

Write to SEN bit occurs here

Set S bit (SSPSTAT)

    and sets SSPIF bit