Microchip Technology MCP1631RD-MCC2 Data Sheet
2006-2012 Microchip Technology Inc.
DS41291G-page 201
PIC16F882/883/884/886/887
13.4.7
I
2
C™ MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
(SSPCON2 register) is programmed high and the I
(SSPCON2 register) is programmed high and the I
2
C
logic module is in the Idle state. When the RSEN bit is
set, the SCL pin is asserted low. When the SCL pin is
sampled low, the Baud Rate Generator is loaded with
the contents of SSPADD<5:0> and begins counting.
The SDA pin is released (brought high) for one Baud
Rate Generator count (T
set, the SCL pin is asserted low. When the SCL pin is
sampled low, the Baud Rate Generator is loaded with
the contents of SSPADD<5:0> and begins counting.
The SDA pin is released (brought high) for one Baud
Rate Generator count (T
BRG
). When the Baud Rate
Generator times out, if SDA is sampled high, the SCL
pin will be de-asserted (brought high). When SCL is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPADD<6:0> and begins count-
ing. SDA and SCL must be sampled high for one T
pin will be de-asserted (brought high). When SCL is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPADD<6:0> and begins count-
ing. SDA and SCL must be sampled high for one T
BRG
.
This action is then followed by assertion of the SDA pin
(SDA = 0) for one T
(SDA = 0) for one T
BRG
, while SCL is high. Following
this, the RSEN bit (SSPCON2 register) will be automat-
ically cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT register) will be set. The SSPIF bit
will not be set until the Baud Rate Generator has timed
out.
ically cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT register) will be set. The SSPIF bit
will not be set until the Baud Rate Generator has timed
out.
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode), or eight bits of data (7-bit
mode).
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode), or eight bits of data (7-bit
mode).
13.4.7.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 13-14:
REPEAT START CONDITION WAVEFORM
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
• SDA is sampled low when SCL goes
from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data “1”.
another master is attempting to
transmit a data “1”.
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
SDA
SCL
Sr = Repeated Start
Write to SSPCON2
Write to SSPBUF occurs here
Falling edge of ninth clock
End of Xmit
At completion of Start bit,
hardware clear RSEN bit
hardware clear RSEN bit
1st bit
Set S (SSPSTAT<3>)
T
BRG
T
BRG
SDA = 1,
SDA = 1,
SCL (no change)
SCL = 1
occurs here,
T
BRG
T
BRG
T
BRG
and set SSPIF