Microchip Technology MCP1631RD-MCC2 Data Sheet
PIC16F882/883/884/886/887
DS41291G-page 28
2006-2012 Microchip Technology Inc.
TABLE 2-1:
PIC16F882/883/884/886/887
SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other Resets
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
xxxx xxxx
01h
TMR0
Timer0 Module Register
xxxx xxxx
uuuu uuuu
02h
PCL
Program Counter’s (PC) Least Significant Byte
0000 0000
0000 0000
03h
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
(5)
04h
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
uuuu uuuu
05h
PORTA
(3)
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx xxxx
0000 0000
06h
PORTB
(3)
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
0000 0000
07h
PORTC
(3)
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
0000 0000
08h
PORTD
(3,4)
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
0000 0000
09h
PORTE
(3)
—
—
—
—
RE3
RE2
(4)
RE1
(4)
RE0
(4)
---- xxxx
---- 0000
0Ah
PCLATH
—
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000
---0 0000
0Bh
INTCON
GIE PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
(1)
0000 000x
0000 000u
0Ch
PIR1
—
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
-000 0000
0000 0000
0Dh
PIR2
OSFIF
C2IF
C1IF
EEIF
BCLIF
ULPWUIF
—
CCP2IF
0000 00-0
0000 0000
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
10h
T1CON
T1GINV
TMR1GE
T1CKPS1
T1CKPS0 T1OSCEN
T1SYNC
TMR1CS
TMR1ON
0000 0000
uuuu uuuu
11h
TMR2
Timer2 Module Register
0000 0000
0000 0000
12h
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0
TMR2ON
T2CKPS1 T2CKPS0 -000 0000
-000 0000
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
uuuu uuuu
14h
SSPCON
(2)
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
0000 0000
15h
CCPR1L
Capture/Compare/PWM Register 1 Low Byte (LSB)
xxxx xxxx
uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM Register 1 High Byte (MSB)
xxxx xxxx
uuuu uuuu
17h
CCP1CON
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
0000 0000
0000 0000
18h
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 0000
19h
TXREG
EUSART Transmit Data Register
0000 0000
0000 0000
1Ah
RCREG
EUSART Receive Data Register
0000 0000
0000 0000
1Bh
CCPR2L
Capture/Compare/PWM Register 2 Low Byte (LSB)
xxxx xxxx
uuuu uuuu
1Ch
CCPR2H
Capture/Compare/PWM Register 2 High Byte (MSB)
xxxx xxxx
uuuu uuuu
1Dh
CCP2CON
—
—
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
--00 000
1Eh
ADRESH
A/D Result Register High Byte
xxxx xxxx
uuuu uuuu
1Fh
ADCON0
ADCS1
ADCS0
CHS3
CHS2
CHS1
CHS0
GO/
DONE
ADON
0000 0000
00-0 0000
Legend:
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note
1:
MCLR and WDT Reset do not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the
mismatch exists.
mismatch exists.
2:
When SSPCON register bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed through the SSPMSK
register. See Registers
and
for more details.
3:
Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the data
latches are either undefined (POR) or unchanged (other Resets).
4:
PIC16F884/PIC16F887 only.
5:
See
for Reset value for specific condition.