Microchip Technology MCP1631RD-MCC2 Data Sheet

DS41291G-page 96

 2006-2012 Microchip Technology Inc.

There are three additional comparator features:
• Timer1 count enable (gate)
• Synchronizing output with Timer1
• Simultaneous read of comparator outputs

8.8.1

COMPARATOR C2 GATING TIMER1

This feature can be used to time the duration or interval
of analog events. Clearing the T1GSS bit of the
CM2CON1 register will enable Timer1 to increment
based on the output of Comparator C2. This requires
that Timer1 is on and gating is enabled. See

 for

details.
It is recommended to synchronize the comparator with
Timer1 by setting the C2SYNC bit when the comparator
is used as the Timer1 gate source. This ensures Timer1
does not miss an increment if the comparator changes
during an increment.

8.8.2

SYNCHRONIZING COMPARATOR 
C2 OUTPUT TO TIMER1

The Comparator C2 output can be synchronized with
Timer1 by setting the C2SYNC bit of the CM2CON1
register. When enabled, the C2 output is latched on the
falling edge of the Timer1 clock source. If a prescaler is
used with Timer1, the comparator output is latched after
the prescaling function. To prevent a race condition, the
comparator output is latched on the falling edge of the
Timer1 clock source and Timer1 increments on the
rising edge of its clock source. See the Comparator
Block Diagram (Figures

) and the Timer1

Block Diagram (

) for more information. 

8.8.3

SIMULTANEOUS COMPARATOR 
OUTPUT READ

The MC1OUT and MC2OUT bits of the CM2CON1
register are mirror copies of both comparator outputs.
The ability to read both outputs simultaneously from a
single register eliminates the timing skew of reading
separate registers.

  

Note 1: Obtaining the status of C1OUT or

C2OUT by reading CM2CON1 does not
affect the comparator interrupt mismatch
registers.

R-0

R-0

R/W-0

R/W-0

U-0

U-0

R/W-1

R/W-0

MC1OUT

MC2OUT

C1RSEL

C2RSEL

—

—

T1GSS

C2SYNC

bit 7

bit 0

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

MC1OUT: Mirror Copy of C1OUT bit

bit 6

MC2OUT: Mirror Copy of C2OUT bit

bit 5

C1RSEL: Comparator C1 Reference Select bit
1 = CVREF routed to C1VREF input of Comparator C1
0 = Absolute voltage reference (0.6) routed to C1VREF input of Comparator C1 (or 1.2V precision

reference on parts so equipped)

bit 4

C2RSEL: Comparator C2 Reference Select bit
1 = CVREF routed to C2VREF input of Comparator C2
0 = Absolute voltage reference (0.6) routed to C2VREF input of Comparator C2 (or 1.2V precision

reference on parts so equipped)

bit 3-2

Unimplemented: Read as ‘0’

bit 1

T1GSS: Timer1 Gate Source Select bit
1 = Timer1 gate source is T1G
0 = Timer1 gate source is SYNCC2OUT.

bit 0

C2SYNC: Comparator C2 Output Synchronization bit
1 = Output is synchronous to falling edge of Timer1 clock
0 = Output is asynchronous