Microchip Technology DM164134 Data Sheet

DS41159E-page 124

© 2006 Microchip Technology Inc.

Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.

Table 15-1 shows the timer resources of the CCP
module modes.

In Capture mode, CCPR1H:CCPR1L captures the 16-
bit value of the TMR1 or TMR3 register when an event
occurs on pin RC2/CCP1. An event is defined as:

• every falling edge

• every rising edge

• every 4th rising edge

• every 16th rising edge

An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the
interrupt request flag bit, CCP1IF (PIR registers), is set.
It must be cleared in software. If another capture
occurs before the value in register CCPR1 is read, the
old captured value will be lost.

15.2.1

CCP PIN CONFIGURATION

In Capture mode, the RC2/CCP1 pin should be
configured as an input by setting the TRISC<2> bit.        

15.2.2

TIMER1/TIMER3 MODE SELECTION

The timers used with the capture feature (either Timer1
and/or Timer3) must be running in Timer mode or Syn-
chronized Counter mode. In Asynchronous Counter
mode, the capture operation may not work. The timer
used with each CCP module is selected in the T3CON
register.

Capture

Compare

PWM

Timer1 or Timer3
Timer1 or Timer3

Timer2

If the RC2/CCP1 is configured as an out-
put, a write to the port can cause a capture
condition. 

Capture

Capture

TMR1 or TMR3 time base. Time base can be different for each CCP.

Capture

Compare

The compare could be configured for the special event trigger which clears either TMR1 
or TMR3, depending upon which time base is used.

Compare

Compare

The compare(s) could be configured for the special event trigger which clears TMR1 or 
TMR3, depending upon which time base is used.

PWM

PWM

The PWMs will have the same frequency and update rate (TMR2 interrupt).

PWM

Capture

None.

PWM

Compare

None.