Microchip Technology DM164134 Data Sheet
PIC18FXX8
DS41159E-page 132
© 2006 Microchip Technology Inc.
16.1
ECCP1 Module
Enhanced Capture/Compare/PWM Register 1 (ECCPR1)
is comprised of two 8-bit registers: ECCPR1L (low
byte) and ECCPR1H (high byte). The ECCP1CON
register controls the operation of ECCP1; the additional
registers, ECCPAS and ECCP1DEL, control Enhanced
PWM specific features. All registers are readable and
writable.
is comprised of two 8-bit registers: ECCPR1L (low
byte) and ECCPR1H (high byte). The ECCP1CON
register controls the operation of ECCP1; the additional
registers, ECCPAS and ECCP1DEL, control Enhanced
PWM specific features. All registers are readable and
writable.
Table 16-1 shows the timer resources for the ECCP
module modes. Table 16-2 describes the interactions
of the ECCP module with the standard CCP module.
module modes. Table 16-2 describes the interactions
of the ECCP module with the standard CCP module.
In PWM mode, the ECCP module can have up to four
available outputs, depending on which operating mode
is selected. These outputs are multiplexed with PORTD
and the Parallel Slave Port. Both the operating mode
and the output pin assignments are configured by setting
PWM output configuration bits, EPWM1M1:EPWM1M0
(ECCP1CON<7:6>). The specific pin assignments for
the various output modes are shown in Table 16-3.
available outputs, depending on which operating mode
is selected. These outputs are multiplexed with PORTD
and the Parallel Slave Port. Both the operating mode
and the output pin assignments are configured by setting
PWM output configuration bits, EPWM1M1:EPWM1M0
(ECCP1CON<7:6>). The specific pin assignments for
the various output modes are shown in Table 16-3.
TABLE 16-1:
ECCP1 MODE – TIMER
RESOURCE
RESOURCE
TABLE 16-2:
INTERACTION OF CCP1 AND ECCP1 MODULES
TABLE 16-3:
PIN ASSIGNMENTS FOR VARIOUS ECCP MODES
ECCP1 Mode
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer1 or Timer3
Timer2
ECCP1 Mode
CCP1 Mode
Interaction
Capture
Capture
TMR1 or TMR3 time base. Time base can be different for each CCP.
Capture
Compare
The compare could be configured for the special event trigger which clears either
TMR1 or TMR3 depending upon which time base is used.
TMR1 or TMR3 depending upon which time base is used.
Compare
Compare
The compare(s) could be configured for the special event trigger which clears TMR1
or TMR3 depending upon which time base is used.
or TMR3 depending upon which time base is used.
PWM
PWM
The PWMs will have the same frequency and update rate (TMR2 interrupt).
PWM
Capture
None
PWM
Compare
None
ECCP Mode
(1)
ECCP1CON
Configuration
RD4
RD5
RD6
RD7
Conventional CCP Compatible
00xx11xx
ECCP1
RD<5>,
PSP<5>
RD<6>,
PSP<6>
RD<7>,
PSP<7>
Dual Output PWM
(2)
10xx11xx
P1A
P1B
RD<6>,
PSP<6>
RD<7>,
PSP<7>
Quad Output PWM
(2)
x1xx11xx
P1A
P1B
P1C
P1D
Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode.
Note 1:
In all cases, the appropriate TRISD bits must be cleared to make the corresponding pin an output.
2:
In these modes, the PSP I/O control for PORTD is overridden by P1B, P1C and P1D.