Microchip Technology DM164134 Data Sheet
© 2006 Microchip Technology Inc.
DS41159E-page 167
PIC18FXX8
17.4.6
MASTER MODE
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I
2
C bus may be taken when the P bit is
set or the bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I
conducts all I
2
C bus operations based on Start and
Stop bit conditions.
Once Master mode is enabled, the user has six
options.
options.
1.
Assert a Start condition on SDA and SCL.
2.
Assert a Repeated Start condition on SDA and
SCL.
SCL.
3.
Write to the SSPBUF register initiating
transmission of data/address.
transmission of data/address.
4.
Configure the I
2
C port to receive data.
5.
Generate an Acknowledge condition at the end
of a received byte of data.
of a received byte of data.
6.
Generate a Stop condition on SDA and SCL.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP interrupt if enabled):
SSPIF, to be set (SSP interrupt if enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
FIGURE 17-16:
MSSP BLOCK DIAGRAM (I
2
C™ MASTER MODE)
Note:
The MSSP module, when configured in
I
I
2
C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
Read
Write
SSPSR
Start bit, Stop bit,
SSPBUF
Internal
Data Bus
Set/Reset S, P, WCOL (SSPSTAT);
Shift
Clock
MSb
LSb
SDA
Acknowledge
Generate
SCL
SCL in
Bus Collision
SDA in
Receiv
e E
nable
Cloc
k
Cntl
C
loc
k Arbit
rat
e/
W
C
O
L
Det
e
ct
(hold of
f clock
s
ource)
SSPADD<6:0>
Baud
set SSPIF, BCLIF;
reset ACKSTAT, PEN (SSPCON2)
reset ACKSTAT, PEN (SSPCON2)
Rate
Generator
SSPM3:SSPM0
Start bit Detect
Stop bit Detect
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV