Microchip Technology DM164134 Data Sheet
© 2006 Microchip Technology Inc.
DS41159E-page 169
PIC18FXX8
17.4.7
BAUD RATE GENERATOR
In I
2
C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 17-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to 0 and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (T
SSPADD register (Figure 17-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to 0 and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (T
CY
) on the
Q2 and Q4 clocks. In I
2
C Master mode, the BRG is
reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
FIGURE 17-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
TABLE 17-3:
I
2
C™ CLOCK RATE w/BRG
SSPM3:SSPM0
BRG Down Counter
CLKO
F
OSC
/4
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control
Reload
F
OSC
F
CY
F
CY
* 2
BRG Value
F
SCL
(2 Rollovers of BRG)
40 MHz
10 MHz
20 MHz
18h
400 kHz
(1)
40 MHz
10 MHz
20 MHz
1Fh
312.5 kHz
40 MHz
10 MHz
20 MHz
63h
100 kHz
16 MHz
4 MHz
8 MHz
09h
400 kHz
(1)
16 MHz
4 MHz
8 MHz
0Ch
308 kHz
16 MHz
4 MHz
8 MHz
27h
100 kHz
4 MHz
1 MHz
2 MHz
02h
333 kHz
(1)
4 MHz
1 MHz
2 MHz
09h
100kHz
4 MHz
1 MHz
2 MHz
00h
1 MHz
(1)
Note 1:
The I
2
C™ interface does not conform to the 400 kHz I
2
C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.