Microchip Technology DM164134 Data Sheet
PIC18FXX8
DS41159E-page 22
© 2006 Microchip Technology Inc.
If the main oscillator is configured for HS4 (PLL) mode,
an oscillator start-up time (T
an oscillator start-up time (T
OST
) plus an additional PLL
time-out (T
PLL
) will occur. The PLL time-out is typically
2 ms and allows the PLL to lock to the main oscillator
frequency. A timing diagram indicating the transition
from the Timer1 oscillator to the main oscillator for HS4
mode is shown in Figure 2-9.
frequency. A timing diagram indicating the transition
from the Timer1 oscillator to the main oscillator for HS4
mode is shown in Figure 2-9.
If the main oscillator is configured in the RC, RCIO, EC
or ECIO modes, there is no oscillator start-up time-out.
Operation will resume after eight cycles of the main
oscillator have been counted. A timing diagram indicat-
ing the transition from the Timer1 oscillator to the main
oscillator for RC, RCIO, EC and ECIO modes is shown
in Figure 2-10.
or ECIO modes, there is no oscillator start-up time-out.
Operation will resume after eight cycles of the main
oscillator have been counted. A timing diagram indicat-
ing the transition from the Timer1 oscillator to the main
oscillator for RC, RCIO, EC and ECIO modes is shown
in Figure 2-10.
FIGURE 2-9:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)
FIGURE 2-10:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q4
Q1
Q1 Q2 Q3 Q4 Q1 Q2
OSC1
Internal System
SCS
(OSCCON<0>)
Program
PC
PC + 2
Note 1: T
OST
= 1024 T
OSC
(drawing not to scale).
T1OSI
Clock
T
OST
Q3
PC + 4
T
PLL
T
OSC
T
T
1
P
T
SCS
Q4
OSC2
PLL Clock
Input
1
2
3
4
5
6
7
8
Counter
Q3
Q4
Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3
OSC1
Internal System
SCS
(OSCCON<0>)
Program
PC
PC + 2
Note 1: RC Oscillator mode assumed.
PC + 4
T1OSI
Clock
OSC2
Q4
T
T
1
P
T
OSC
T
SCS
1
2
3
4
5
6
7
8
Counter