Microchip Technology DM164134 Data Sheet
© 2006 Microchip Technology Inc.
DS41159E-page 23
PIC18FXX8
2.7
Effects of Sleep Mode on the
On-Chip Oscillator
On-Chip Oscillator
When the device executes a SLEEP instruction, the
on-chip clocks and oscillator are turned off and the
device is held at the beginning of an instruction cycle
(Q1 state). With the oscillator off, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor
switching currents have been removed, Sleep mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during Sleep will increase the current
consumed during Sleep. The user can wake from
Sleep through external Reset, Watchdog Timer Reset
or through an interrupt.
on-chip clocks and oscillator are turned off and the
device is held at the beginning of an instruction cycle
(Q1 state). With the oscillator off, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor
switching currents have been removed, Sleep mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during Sleep will increase the current
consumed during Sleep. The user can wake from
Sleep through external Reset, Watchdog Timer Reset
or through an interrupt.
2.8
Power-up Delays
Power-up delays are controlled by two timers so that no
external Reset circuitry is required for most applica-
tions. The delays ensure that the device is kept in
external Reset circuitry is required for most applica-
tions. The delays ensure that the device is kept in
Reset until the device power supply and clock are
stable. For additional information on Reset operation,
see Section 3.0 “Reset”.
stable. For additional information on Reset operation,
see Section 3.0 “Reset”.
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of T
optionally provides a fixed delay of T
PWRT
#D033) on power-up only (POR and BOR). The second
timer is the Oscillator Start-up Timer (OST), intended to
keep the chip in Reset until the crystal oscillator is
stable.
timer is the Oscillator Start-up Timer (OST), intended to
keep the chip in Reset until the crystal oscillator is
stable.
With the PLL enabled (HS4 Oscillator mode), the time-
out sequence following a Power-on Reset is different
from other oscillator modes. The time-out sequence is
as follows: the PWRT time-out is invoked after a POR
time delay has expired, then the Oscillator Start-up
Timer (OST) is invoked. However, this is still not a
sufficient amount of time to allow the PLL to lock at high
frequencies. The PWRT timer is used to provide an
additional fixed 2 ms (nominal) to allow the PLL ample
time to lock to the incoming clock frequency.
out sequence following a Power-on Reset is different
from other oscillator modes. The time-out sequence is
as follows: the PWRT time-out is invoked after a POR
time delay has expired, then the Oscillator Start-up
Timer (OST) is invoked. However, this is still not a
sufficient amount of time to allow the PLL to lock at high
frequencies. The PWRT timer is used to provide an
additional fixed 2 ms (nominal) to allow the PLL ample
time to lock to the incoming clock frequency.
TABLE 2-3:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC Mode
OSC1 Pin
OSC2 Pin
RC
Floating, external resistor should pull high
At logic low
RCIO
Floating, external resistor should pull high
Configured as PORTA, bit 6
ECIO
Floating
Configured as PORTA, bit 6
EC
Floating
At logic low
LP, XT and HS
Feedback inverter disabled at quiescent
voltage level
voltage level
Feedback inverter disabled at quiescent
voltage level
voltage level
Note:
See Table 3-1 in Section 3.0 “Reset” for time-outs due to Sleep and MCLR Reset.