Microchip Technology DM164134 Data Sheet

© 2006 Microchip Technology Inc.

DS41159E-page 265

There are several features intended to maximize
system reliability, minimize cost through elimination of
external components, provide power-saving operating
modes and offer code protection. These are:

• Oscillator Selection

• Reset

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

• Watchdog Timer (WDT)

• Sleep

• Code Protection

• ID Locations

• In-Circuit Serial Programming

All PIC18FXX8 devices have a Watchdog Timer which
is permanently enabled via the configuration bits or
software controlled. It runs off its own RC oscillator for
added reliability. There are two timers that offer
necessary delays on power-up. One is the Oscillator
Start-up Timer (OST), intended to keep the chip in
Reset until the crystal oscillator is stable. The other is
the Power-up Timer (PWRT) which provides a fixed
delay on power-up only, designed to keep the part in
Reset while the power supply stabilizes. With these two
timers on-chip, most applications need no external
Reset circuitry. 

Sleep mode is designed to offer a very Low-Current
Power-Down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer wake-up or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits is used to select various options.

The configuration bits can be programmed (read as ‘0’)
or left unprogrammed (read as ‘1’), to select various
device configurations. These bits are mapped starting
at program memory location 300000h.

The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh)
which can only be accessed using table reads and
table writes.

Programming the Configuration registers is done in a
manner similar to programming the Flash memory. The
EECON1 register WR bit starts a self-timed write to the
Configuration register. In normal operation mode, a
TBLWT

 instruction, with the TBLPTR pointed to the

Configuration register, sets up the address and the
data for the Configuration register write. Setting the WR
bit starts a long

 write to the Configuration register. The

Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWT instruction
can write a ‘1’ or a ‘0’ into the cell.

300001h

CONFIG1H

—

—

OSCSEN

—

—

FOSC2

FOSC1

FOSC0

--1- -111

300002h

CONFIG2L

—

—

—

—

BORV1

BORV0

BOREN

PWRTEN

---- 1111

300003h

CONFIG2H

—

—

—

—

WDTPS2

WDTPS1

WDTPS0

WDTEN

---- 1111

300006h

CONFIG4L

DEBUG

—

—

—

—

LVP

—

STVREN

1--- -1-1

300008h

CONFIG5L

—

—

—

—

CP3

CP2

CP1

CP0

---- 1111

300009h

CONFIG5H

CPD

CPB

—

—

—

—

—

—

11-- ----

30000Ah

CONFIG6L

—

—

—

—

WRT3

WRT2

WRT1

WRT0

---- 1111

30000Bh

CONFIG6H

WRTD

WRTB

WRTC

—

—

—

—

—

111- ----

30000Ch

CONFIG7L

—

—

—

—

EBTR3

EBTR2

EBTR1

EBTR0

---- 1111

30000Dh

CONFIG7H

—

EBTRB

—

—

—

—

—

—

-1-- ----

3FFFFEh

DEVID1

DEV2

DEV1

DEV0

REV4

REV3

REV2

REV1

REV0

3FFFFFh

DEVID2

DEV10

DEV9

DEV8

DEV7

DEV6

DEV5

DEV4

DEV3

0000 1000

x

 = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.

See Register 24-11 for DEVID1 values.