Microchip Technology DM164134 Data Sheet
© 2006 Microchip Technology Inc.
DS41159E-page 267
PIC18FXX8
REGISTER 24-3:
CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
REGISTER 24-4:
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
U-0
U-0
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
—
—
—
—
WDTPS2
WDTPS1
WDTPS0
WDTEN
bit 7
bit 0
bit 7-4
Unimplemented: Read as ‘0’
bit 3-1
WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits
111
= 1:128
110
= 1:64
101
= 1:32
100
= 1:16
011
= 1:8
010
= 1:4
001
= 1:2
000
= 1:1
Note:
The Watchdog Timer postscale select bits configuration used in the PIC18FXXX
devices has changed from the configuration used in the PIC18CXXX devices.
devices has changed from the configuration used in the PIC18CXXX devices.
bit 0
WDTEN: Watchdog Timer Enable bit
1
= WDT enabled
0
= WDT disabled (control is placed on the SWDTEN bit)
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
R/P-1
U-0
U-0
U-0
U-0
R/P-1
U-0
R/P-1
DEBUG
—
—
—
—
LVP
—
STVREN
bit 7
bit 0
bit 7
DEBUG: Background Debugger Enable bit
1
= Background Debugger disabled. RB6 and RB7 configured as general purpose I/O pins.
0
= Background Debugger enabled. RB6 and RB7 are dedicated to In-Circuit Debug.
bit 6-3
Unimplemented: Read as ‘0’
bit 2
LVP: Low-Voltage ICSP Enable bit
1
= Low-Voltage ICSP enabled
0
= Low-Voltage ICSP disabled
bit 1
Unimplemented: Read as ‘0’
bit 0
STVREN: Stack Full/Underflow Reset Enable bit
1
= Stack Full/Underflow will cause Reset
0
= Stack Full/Underflow will not cause Reset
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state