Microchip Technology DM164134 Data Sheet
PIC18FXX8
DS41159E-page 272
© 2006 Microchip Technology Inc.
24.2
Watchdog Timer (WDT)
The Watchdog Timer is a free running, on-chip RC
oscillator which does not require any external com-
ponents. This RC oscillator is separate from the RC
oscillator of the OSC1/CLKI pin. That means that the
WDT will run, even if the clock on the OSC1/CLKI and
OSC2/CLKO/RA6 pins of the device has been stopped,
for example, by execution of a SLEEP instruction.
oscillator which does not require any external com-
ponents. This RC oscillator is separate from the RC
oscillator of the OSC1/CLKI pin. That means that the
WDT will run, even if the clock on the OSC1/CLKI and
OSC2/CLKO/RA6 pins of the device has been stopped,
for example, by execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device Reset (Watchdog Timer Reset). If the device is
in Sleep mode, a WDT time-out causes the device to
wake-up and continue with normal operation
(Watchdog Timer wake-up). The TO bit in the RCON
register will be cleared upon a WDT time-out.
device Reset (Watchdog Timer Reset). If the device is
in Sleep mode, a WDT time-out causes the device to
wake-up and continue with normal operation
(Watchdog Timer wake-up). The TO bit in the RCON
register will be cleared upon a WDT time-out.
The Watchdog Timer is enabled/disabled by a device
configuration bit. If the WDT is enabled, software
execution may not disable this function. When the
WDTEN configuration bit is cleared, the SWDTEN bit
enables/disables the operation of the WDT.
configuration bit. If the WDT is enabled, software
execution may not disable this function. When the
WDTEN configuration bit is cleared, the SWDTEN bit
enables/disables the operation of the WDT.
The WDT time-out period values may be found in
Section 27.0 “Electrical Characteristics” under
parameter #31. Values for the WDT postscaler may be
assigned using the configuration bits.
Section 27.0 “Electrical Characteristics” under
parameter #31. Values for the WDT postscaler may be
assigned using the configuration bits.
24.2.1
CONTROL REGISTER
Register 24-13 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
configuration bit only when the configuration bit has
disabled the WDT.
readable and writable register which contains a control
bit that allows software to override the WDT enable
configuration bit only when the configuration bit has
disabled the WDT.
REGISTER 24-13: WDTCON: WATCHDOG TIMER CONTROL REGISTER
Note:
The CLRWDT and SLEEP instructions clear
the WDT and the postscaler if assigned to
the WDT and prevent it from timing out
and generating a device Reset condition.
the WDT and the postscaler if assigned to
the WDT and prevent it from timing out
and generating a device Reset condition.
Note:
When a CLRWDT instruction is executed
and the postscaler is assigned to the WDT,
the postscaler count will be cleared but the
postscaler assignment is not changed.
and the postscaler is assigned to the WDT,
the postscaler count will be cleared but the
postscaler assignment is not changed.
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
SWDTEN
bit 7
bit 0
bit 7-1
Unimplemented: Read as ‘0’
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit
1
= Watchdog Timer is on
0
= Watchdog Timer is turned off if the WDTEN configuration bit in the Configuration register = 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR