Microchip Technology DM164134 Data Sheet
PIC18FXX8
DS41159E-page 274
© 2006 Microchip Technology Inc.
24.3
Power-Down Mode (Sleep)
Power-down mode is entered by executing a SLEEP
instruction.
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (RCON<2>) is cleared, the
TO bit (RCON<3>) is set and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low or high-impedance).
keeps running, the PD bit (RCON<2>) is cleared, the
TO bit (RCON<3>) is set and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low or high-impedance).
For lowest current consumption in this mode, place all
I/O pins at either V
I/O pins at either V
DD
or V
SS
, ensure no external circuitry
is drawing current from the I/O pin, power-down the A/D
and disable external clocks. Pull all I/O pins that are
high-impedance inputs, high or low externally, to avoid
switching currents caused by floating inputs. The T0CKI
input should also be at V
and disable external clocks. Pull all I/O pins that are
high-impedance inputs, high or low externally, to avoid
switching currents caused by floating inputs. The T0CKI
input should also be at V
DD
or V
SS
for lowest current
consumption. The contribution from on-chip pull-ups on
PORTB should be considered.
PORTB should be considered.
The MCLR pin must be at a logic high level (V
IHMC
).
24.3.1
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the
following events:
following events:
1.
External Reset input on MCLR pin.
2.
Watchdog Timer wake-up (if WDT was
enabled).
enabled).
3.
Interrupt from INT pin, RB port change or a
peripheral interrupt.
peripheral interrupt.
The following peripheral interrupts can wake the device
from Sleep:
from Sleep:
1.
PSP read or write.
2.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
asynchronous counter.
3.
TMR3 interrupt. Timer3 must be operating as an
asynchronous counter.
asynchronous counter.
4.
CCP Capture mode interrupt.
5.
Special event trigger (Timer1 in Asynchronous
mode using an external clock).
mode using an external clock).
6.
MSSP (Start/Stop) bit detect interrupt.
7.
MSSP transmit or receive in Slave mode
(SPI/I
(SPI/I
2
C).
8.
USART RX or TX (Synchronous Slave mode).
9.
A/D conversion (when A/D clock source is RC).
10. EEPROM write operation complete.
11. LVD interrupt.
Other peripherals cannot generate interrupts, since
during Sleep, no on-chip clocks are present.
during Sleep, no on-chip clocks are present.
External MCLR Reset will cause a device Reset. All
other events are considered a continuation of program
execution and will cause a “wake-up”. The TO and PD
bits in the RCON register can be used to determine the
cause of the device Reset. The PD bit, which is set on
power-up, is cleared when Sleep is invoked. The TO bit
is cleared if a WDT time-out occurred (and caused
wake-up).
other events are considered a continuation of program
execution and will cause a “wake-up”. The TO and PD
bits in the RCON register can be used to determine the
cause of the device Reset. The PD bit, which is set on
power-up, is cleared when Sleep is invoked. The TO bit
is cleared if a WDT time-out occurred (and caused
wake-up).
When the SLEEP instruction is being executed, the next
instruction (PC + 2) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
instruction (PC + 2) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
24.3.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If an interrupt condition (interrupt flag bit and
interrupt enable bits are set) occurs before the
execution of a SLEEP instruction, the SLEEP
instruction will complete as a NOP. Therefore, the
WDT and WDT postscaler will not be cleared, the
TO bit will not be set and the PD bit will not be
cleared.
execution of a SLEEP instruction, the SLEEP
instruction will complete as a NOP. Therefore, the
WDT and WDT postscaler will not be cleared, the
TO bit will not be set and the PD bit will not be
cleared.
• If the interrupt condition occurs during or after
the execution of a SLEEP instruction, the device
will immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
will immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP
SLEEP
instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT
instruction should be executed before a SLEEP
instruction.
instruction should be executed before a SLEEP
instruction.