Microchip Technology DM164134 Data Sheet
PIC18FXX8
DS41159E-page 354
© 2006 Microchip Technology Inc.
TABLE 27-18: I
2
C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
100
T
HIGH
Clock High Time
100 kHz mode
4.0
—
μs
PIC18FXX8 must operate
at a minimum of 1.5 MHz
at a minimum of 1.5 MHz
400 kHz mode
0.6
—
μs
PIC18FXX8 must operate
at a minimum of 10 MHz
at a minimum of 10 MHz
SSP Module
1.5 T
CY
—
101
T
LOW
Clock Low Time
100 kHz mode
4.7
—
μs
PIC18FXX8 must operate
at a minimum of 1.5 MHz
at a minimum of 1.5 MHz
400 kHz mode
1.3
—
μs
PIC18FXX8 must operate
at a minimum of 10 MHz
at a minimum of 10 MHz
SSP module
1.5 T
CY
—
ns
102
T
R
SDA and SCL Rise
Time
Time
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 C
B
300
ns
C
B
is specified to be from
10 to 400 pF
103
T
F
SDA and SCL Fall
Time
Time
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1 C
B
300
ns
C
B
is specified to be from
10 to 400 pF
90
T
SU
:
STA
Start Condition
Setup Time
Setup Time
100 kHz mode
4.7
—
μs
Only relevant for Repeated
Start condition
Start condition
400 kHz mode
0.6
—
μs
91
T
HD
:
STA
Start Condition
Hold Time
Hold Time
100 kHz mode
4.0
—
μs
After this period the first
clock pulse is generated
clock pulse is generated
400 kHz mode
0.6
—
μs
106
T
HD
:
DAT
Data Input Hold
Time
Time
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
μs
107
T
SU
:
DAT
Data Input Setup
Time
Time
100 kHz mode
250
—
ns
(Note 2)
400 kHz mode
100
—
ns
92
T
SU
:
STO
Stop Condition
Setup Time
Setup Time
100 kHz mode
4.7
—
μs
400 kHz mode
0.6
—
μs
109
T
AA
Output Valid from
Clock
Clock
100 kHz mode
—
3500
ns
(Note 1)
400 kHz mode
—
—
ns
110
T
BUF
Bus Free Time
100 kHz mode
4.7
—
μs
Time the bus must be free
before a new transmission
can start
before a new transmission
can start
400 kHz mode
1.3
—
μs
D102
C
B
Bus Capacitive Loading
—
400
pF
Note 1:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2:
A Fast mode I
2
C™ bus device can be used in a Standard mode I
2
C bus system, but the requirement
T
SU
;
DAT
≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the
low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output
the next data bit to the SDA line.
Before the SCL line is released, T
the next data bit to the SDA line.
Before the SCL line is released, T
R
max. + T
SU
:
DAT
= 1000 + 250 = 1250 ns (according to the Standard
mode I
2
C bus specification).