Microchip Technology DM183037 Data Sheet
PIC18F97J94 FAMILY
DS30575A-page 188
2012 Microchip Technology Inc.
REGISTER 10-18: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TMR5GIP
LCDIP
RC2IP
TX2IP
CTMUIP
CCP2IP
CCP1IP
RTCCIP
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
TMR5GIP: TMR5 Gate Interrupt Priority bit
1 = High priority
0 = Low priority
1 = High priority
0 = Low priority
bit 6
LCDIP: LCD Ready Interrupt Priority bit
1 = High priority
0 = Low priority
1 = High priority
0 = Low priority
bit 5
RC2IP: EUSART2 Receive Priority Flag bit
1 = High priority
0 = Low priority
1 = High priority
0 = Low priority
bit 4
TX2IP: EUSART2 Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
1 = High priority
0 = Low priority
bit 3
CTMUIP: CTMU Interrupt Priority bit
1 = High priority
0 = Low priority
1 = High priority
0 = Low priority
bit 2
CCP2IP: CCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
1 = High priority
0 = Low priority
bit 1
CCP1IP: ECCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
1 = High priority
0 = Low priority
bit 0
RTCCIP: RTCC Interrupt Priority bit
1 = High priority
0 = Low priority
1 = High priority
0 = Low priority