Microchip Technology DM183037 Data Sheet
2012 Microchip Technology Inc.
DS30575A-page 225
PIC18F97J94 FAMILY
FIGURE 11-6:
STRUCTURE OF PORT SHARED WITH PPS PERIPHERALS
I/O TRIS Enable
Q
D
CK
WR LAT/
TRIS Latch
I/O Pin
WR PORT
Data Bus
Q
D
CK
Data Latch
Read PORT
Read TRIS
n
0
WR TRIS
Peripheral 2 Output Enable
I/O
Peripheral ‘n’ Output Enable
PIO Module
Output Multiplexers
Output Function
Read LAT
0
1
Open-Drain Selection
Peripheral Input
Q
Peripheral 1 Output Enable
0
n
1
1
Peripheral Pin Select
0
n
I/O Pin 0
I/O Pin 1
I/O Pin n
1
Peripheral Input
Pin Selection
Select for the Pin
Peripheral ‘n’ Output Data
Peripheral 2 Output Data
Peripheral 1 Output Data
I/O LAT/PORT Data