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Microchip Technology DM183037 Data Sheet

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 2012 Microchip Technology Inc.
DS30575A-page 287
PIC18F97J94 FAMILY
15.2
Timer1/3/5 Operation
Timer1, Timer3 and Timer5 can operate in these
modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
• Timer with Gated Control
The operating mode is determined by the clock select
bits, TMRxCSx (TxCON<7:6>). When the TMRxCSx bits
are cleared (= 00), Timer1/3/5 increments on every inter-
nal instruction cycle (F
OSC
/4). When TMRxCSx = 01, the
Timer1/3/5 clock source is the system clock (F
OSC
).
When it is ‘10’, Timer1/3/5 works as a counter from the
external clock from the TxCKI pin (on the rising edge after
the first falling edge) or the SOSC Oscillator. When it is
‘11’, the Timer1/3/5 clock source is INTOSC.
FIGURE 15-1:
TIMER1/3/5 BLOCK DIAGRAM 
TMR3H
TMR3L
T3SYNC
T3CKPS<1:0>
0
1
Synchronized
Clock Input
2
Set Flag bit
TMR3IF on
Overflow
TMR3
(2)
TMR3ON
Note 1:
ST buffer is a high-speed type when using T3CKI.
2:
Timer3 registers increment on the rising edge.
3:
Synchronization does not operate while in Sleep.
4:
The output of SOSC is determined by the SOSCSEL Configuration bits.
T3G
SOSC
F
OSC
/4
Internal
Clock
SOSCO/SCLKI
SOSCI
1
0
T3CKI
TMR3CS<1:0>
(1)
Synchronize
(3)
det
Sleep Input
TMR3GE
0
1
00
01
10
11
From TMR4
T3GPOL
D
Q
CK
Q
0
1
T3GVAL
T3GTM
T3GSPM
T3GGO/
T3GSS<1:0>
EN
OUT
(4)
10
00
01
F
OSC
Internal
Clock
From Comparator 2
Match PR4
R
Q1
RD
T3GCON
Data Bus
Interrupt
TMR3GIF
Set
T3CLK
F
OSC
/2
Internal
Clock
D
EN
Q
T3G_IN
TMR3ON
Output
01
Timer3 Clock
is INTOSC
Single Pulse
Acq. Control
T3DONE
Prescaler
1, 2, 4, 8
From Comparator 1
Output
T1CON.SOSCEN
T1CON.SOSCEN
SOSCGO
NOSC<2:0> = 100
D
EN
Q
det