Microchip Technology DM183037 Data Sheet

 2012 Microchip Technology Inc.

DS30575A-page 349

19.4.2

PWM DUTY CYCLE

The PWM duty cycle is specified, to use CCP4 as an
example, by writing to the CCPR4L register and to the
CCP4CON<5:4> bits. Up to 10-bit resolution is avail-
able. The CCPR4L contains the eight MSbs and the
CCP4CON<5:4> contains the two LSbs. This 10-bit
value is represented by CCPR4L:CCP4CON<5:4>.
The following equation is used to calculate the PWM
duty cycle in time:

CCPR4L and CCP4CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR4H until after a match between PR2 and TMR2
occurs (that is, the period is complete). In PWM mode,
CCPR4H is a read-only register.

The CCPR4H register and a two-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the CCPR4H and two-bit latch match TMR2,
concatenated with an internal two-bit Q clock or two
bits of the TMR2 prescaler, the CCP4 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:

19.4.3

SETUP FOR PWM OPERATION

To configure the CCP module for PWM operation using
CCP4 as an example:
1.

Set the PWM period by writing to the PR2
register.

2.

Set the PWM duty cycle by writing to the
CCPR4L register and CCP4CON<5:4> bits.

3.

Make the CCP4 pin an output by clearing the
appropriate TRIS bit.

4.

Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.

5.

Configure the CCP4 module for PWM operation.

PWM Duty Cycle = (CCPR4L:CCP4CON<5:4>) •

T

OSC

 • (TMR2 Prescale Value)

If the PWM duty cycle value is longer than
the PWM period, the CCP4 pin will not be
cleared.

F

OSC

F

PWM

---------------









log

2

 

log

-----------------------------bits

=

PWM Resolution (max)

Timer  Prescaler  (1,  4,  16)

16

4

1

1

1

1

PR2 Value

FFh

FFh

FFh

3Fh

1Fh

17h

Maximum Resolution (bits)

10

10

10

8

7

6.58