Microchip Technology DM183037 Data Sheet
PIC18F97J94 FAMILY
DS30575A-page 354
2012 Microchip Technology Inc.
REGISTER 20-2:
SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
)
CKP
SSPM3
SSPM2
(
)
SSPM1
(
)
SSPM0
(
)
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
WCOL: Write Collision Detect bit
1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in
1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0 = No collision
bit 6
SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of
1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of
overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read
the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in
software).
the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in
software).
0 = No overflow
bit 5
SSPEN: Master Synchronous Serial Port Enable bit
(
)
1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
1 = Idle state for the clock is a high level
0 = Idle state for the clock is a low level
1 = Idle state for the clock is a high level
0 = Idle state for the clock is a low level
bit 3-0
SSPM<3:0>: Master Synchronous Serial Port Mode Select bits
(
)
1010 = SPI Master mode: Clock = F
OSC
/(4 * (SSPxADD + 1)
0101 = SPI Slave mode: Clock = SCKx pin; SSx pin control is disabled; SSx can be used as I/O pin
0100 = SPI Slave mode: Clock = SCKx pin; SSx pin control is enabled
0011 = SPI Master mode: Clock = TMR2 output/2
0010 = SPI Master mode: Clock = F
0100 = SPI Slave mode: Clock = SCKx pin; SSx pin control is enabled
0011 = SPI Master mode: Clock = TMR2 output/2
0010 = SPI Master mode: Clock = F
OSC
/64
0001 = SPI Master mode: Clock = F
OSC
/16
0000 = SPI Master mode: Clock = F
OSC
/4
Note 1:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPxBUF register.
writing to the SSPxBUF register.
2:
When enabled, these pins must be properly configured as inputs or outputs.
3:
SSPxADD = 0 is not supported.
4:
Bit combinations not specifically listed here are either reserved or implemented in I
2
C™ mode only.