Microchip Technology DM183037 Data Sheet
2012 Microchip Technology Inc.
DS30575A-page 353
PIC18F97J94 FAMILY
20.3.1
REGISTERS
Each MSSP module has four registers for SPI mode
operation. These are:
• MSSPx Control Register 1 (SSPxCON1)
• MSSPx Status Register (SSPxSTAT)
• MSSPx Control Register 3 (SSPxCON3)
• Serial Receive/Transmit Buffer Register
operation. These are:
• MSSPx Control Register 1 (SSPxCON1)
• MSSPx Status Register (SSPxSTAT)
• MSSPx Control Register 3 (SSPxCON3)
• Serial Receive/Transmit Buffer Register
(SSPxBUF)
• MSSPx Shift Register (SSPxSR) – Not directly
accessible
SSPxCON1, SSPxCON3 and SSPxSTAT are the con-
trol and status registers in SPI mode operation. The
SSPxCON1 and SSPxCON3 registers are readable
and writable. The lower 6 bits of the SSPxSTAT are
read-only. The upper two bits of the SSPxSTAT are
read/write.
trol and status registers in SPI mode operation. The
SSPxCON1 and SSPxCON3 registers are readable
and writable. The lower 6 bits of the SSPxSTAT are
read-only. The upper two bits of the SSPxSTAT are
read/write.
SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data bytes
are written to or read from.
In receive operations, SSPxSR and SSPxBUF
together, create a double-buffered receiver. When
SSPxSR receives a complete byte, it is transferred to
SSPxBUF and the SSPxIF interrupt is set.
During transmission, the SSPxBUF is not double-
buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
out. SSPxBUF is the buffer register to which data bytes
are written to or read from.
In receive operations, SSPxSR and SSPxBUF
together, create a double-buffered receiver. When
SSPxSR receives a complete byte, it is transferred to
SSPxBUF and the SSPxIF interrupt is set.
During transmission, the SSPxBUF is not double-
buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
REGISTER 20-1:
SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE
)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SMP: Sample bit
SPI Master mode:
1 = Input data is sampled at the end of data output time
0 = Input data is sampled at the middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
SPI Master mode:
1 = Input data is sampled at the end of data output time
0 = Input data is sampled at the middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6
CKE: SPI Clock Select bit
(
1 = Transmit occurs on the transition from active to Idle clock state
0 = Transmit occurs on the transition from Idle to active clock state
0 = Transmit occurs on the transition from Idle to active clock state
bit 5
D/A: Data/Address bit
Used in I
Used in I
2
C™ mode only.
bit 4
P: Stop bit
Used in I
Used in I
2
C mode only. This bit is cleared when the MSSPx module is disabled; SSPEN is cleared.
bit 3
S: Start bit
Used in I
Used in I
2
C mode only.
bit 2
R/W: Read/Write Information bit
Used in I
Used in I
2
C mode only.
bit 1
UA: Update Address bit
Used in I
Used in I
2
C mode only.
bit 0
BF: Buffer Full Status bit (Receive mode only)
1 = Receive is complete, SSPxBUF is full
0 = Receive is not complete, SSPxBUF is empty
1 = Receive is complete, SSPxBUF is full
0 = Receive is not complete, SSPxBUF is empty
Note 1:
Polarity of clock state is set by the CKP bit (SSPxCON1<4>).