Microchip Technology DM183037 Data Sheet
PIC18F97J94 FAMILY
DS30575A-page 374
2012 Microchip Technology Inc.
REGISTER 20-7:
SSPxCON1: MSSPx CONTROL REGISTER 1 (I
2
C™ MODE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
)
CKP
SSPM3
SSPM2
(
)
SSPM1
(
)
SSPM0
(
)
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPxBUF register was attempted while the I
In Master Transmit mode:
1 = A write to the SSPxBUF register was attempted while the I
2
C conditions were not valid for a
transmission to be started (must be cleared in software)
0 = No collision
In Slave Transmit mode:
1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in
In Slave Transmit mode:
1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in
In Receive mode:
1 = A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in
software)
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5
SSPEN: Master Synchronous Serial Port Enable bit
(
)
1 = Enables the serial port and configures the SDAx and SCLx pins as the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4
CKP: SCKx Release Control bit
In Slave mode:
1 = Releases clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
In Slave mode:
1 = Releases clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0
SSPM<3:0>: Master Synchronous Serial Port Mode Select bits
(
)
1111 = I
2
C Slave mode: 10-bit address with Start and Stop bit interrupts enabled
1110 = I
2
C Slave mode: 7-bit address with Start and Stop bit interrupts enabled
1011 = I
2
C Firmware Controlled Master mode (slave Idle)
1001 = Load SSPxMSK register at SSPxADD SFR address
(
1000 = I
2
C Master mode: Clock =
F
OSC
/(4 * (SSPxADD + 1))
0111 = I
2
C Slave mode: 10-bit address
)
0110 = I
2
C Slave mode: 7-bit address
Note 1:
When enabled, the SDAx and SCLx pins must be configured as inputs.
2:
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
3:
When SSPM<3:0> = 1001, any reads or writes to the SSPxADD SFR address actually accesses the
SSPxMSK register.
SSPxMSK register.
4:
This mode is only available when 7-Bit Address Masking mode is selected (MSSPMSK Configuration bit
is ‘1’).
is ‘1’).