Microchip Technology DM183037 Data Sheet

 2012 Microchip Technology Inc.

DS30575A-page 391

20.5.7.5

Clock Synchronization and 
the CKP bit

When the CKP bit is cleared, the SCLx output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCLx output low until the SCLx output is already
sampled low. Therefore, the CKP bit will not assert the

SCLx line until an external I

2

C master device has

already asserted the SCLx line. The SCLx output will
remain low until the CKP bit is set and all other devices
on the I

2

C bus have deasserted SCLx. This ensures

that a write to the CKP bit will not violate the minimum
high time requirement for SCLx (see 

).

SDAx

SCLx

DX – 1

DX

WR

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SSPxCON1

CKP

Master Device
Deasserts Clock

Master Device
Asserts Clock