Microchip Technology DM183037 Data Sheet
PIC18F97J94 FAMILY
DS30575A-page 392
2012 Microchip Technology Inc.
FIGURE 20-15:
I
2
C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
SDA
x
SCL
x
S
S
P
xIF
(P
IR1<
3>
or
P
IR3
<
7>
)
BF
(
S
SPx
S
TA
T
<0
>)
SSP
O
V
(
S
SPx
CO
N1
<6
>)
S
1
2
3
4
56
7
8
9
1
23
4
5
6
7
89
1
2
3
4
5
7
8
9
P
A
7
A6
A
5
A4
A
3
A
2
A
1
D7
D6
D5
D4
D3
D2
D1
D
0
D7
D6
D
5
D4
D3
D1
D0
ACK
Re
ce
ivin
g Da
ta
ACK
Re
ce
ivin
g Da
ta
R/W
=
0
ACK
R
e
cei
vi
ng A
ddr
ess
Cle
a
re
d
in
so
ftwa
re
SSP
xBUF
is
re
a
d
B
u
s m
a
st
er
ter
m
inate
s
tra
n
sfer
S
SPO
V
is
s
e
t
b
e
ca
us
e
SS
Px
BUF
is
still fu
ll. ACK
is n
o
t sent
.
D2
6
CKP (
SSPx
CO
N
<
4>
)
CK
P
wr
itte
n
to ‘
1
’ in
If B
F
is
cleare
d
pr
ior to
the fa
llin
g
edg
e
of t
he 9th
cl
ock,
CKP
will n
ot b
e
r
e
se
t
to ‘
0
’ a
nd no
cl
ock
str
e
tch
in
g
will o
ccu
r
softwar
e
Clo
ck
is
h
e
ld
lo
w u
n
til
CK
P
is set to
‘1
’
Clo
ck is n
o
t h
e
ld
lo
w
be
cause b
u
ffer
ful
l bi
t i
s
cl
ear
pr
io
r to
fal
ling ed
ge
of 9th
cl
ock
Clo
ck is n
o
t h
e
ld
lo
w
becau
se A
C
K
=
1
BF
is
se
t a
fte
r
fa
llin
g
edge o
f the 9
th cl
ock,
CK
P
is rese
t to ‘
0
’ a
nd
clock str
e
tch
ing
occu
rs