Microchip Technology DM183037 Data Sheet

Page of 696
 2012 Microchip Technology Inc.
DS30575A-page 529
PIC18F97J94 FAMILY
 
REGISTER 27-2:
UCFG: USB CONFIGURATION REGISTER
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
UTEYE
UOEMON
UPUEN
(
UTRDIS
)
FSEN
(
PPB1
PPB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
UTEYE: USB Eye Pattern Test Enable bit
1 = Eye pattern test is enabled
0 = Eye pattern test is disabled
bit 6
UOEMON: USB OE Monitor Enable bit
1  = UOE signal is active, indicating intervals during which the D+/D- lines are driving
0  = UOE signal is inactive
bit 5
Unimplemented: Read as ‘0’
bit 4
UPUEN: USB On-Chip Pull-up Enable bit
(
1 = On-chip pull-up is enabled (pull-up on D+ with FSEN = 1 or D- with FSEN = 0)
0 = On-chip pull-up is disabled
bit 3
UTRDIS: On-Chip Transceiver Disable bit
)
1 = On-chip transceiver is disabled
0 = On-chip transceiver is active
bit 2
FSEN: Full-Speed Enable bit
1 = Full-speed device: Controls transceiver edge rates; requires input clock at 48 MHz
0 = Low-speed device: Controls transceiver edge rates; requires input clock at 6 MHz
bit 1-0
PPB<1:0>: Ping-Pong Buffers Configuration bits
11 = Even/Odd ping-pong buffers are enabled for Endpoints 1 to 15
10 = Even/Odd ping-pong buffers are enabled for all endpoints
01 = Even/Odd ping-pong buffer are enabled for OUT Endpoint 0
00 = Even/Odd ping-pong buffers are disabled
Note 1:
The UPUEN, UTRDIS and FSEN bits should never be changed while the USB module is enabled. These 
values must be preconfigured prior to enabling the module.
2:
This bit is only valid when the on-chip transceiver is active (UTRDIS = 0); otherwise, it is ignored.
3:
If UTRDIS is set, the UOE signal will be active, independent of the UOEMON bit setting.