Microchip Technology DM183037 Data Sheet
2012 Microchip Technology Inc.
DS30575A-page 531
PIC18F97J94 FAMILY
27.2.3
USB STATUS REGISTER (USTAT)
The USB Status register reports the transaction status
within the SIE. When the SIE issues a USB transfer
complete interrupt, USTAT should be read to determine
the status of the transfer. USTAT contains the transfer
endpoint number, direction and Ping-Pong Buffer
Pointer value (if used).
within the SIE. When the SIE issues a USB transfer
complete interrupt, USTAT should be read to determine
the status of the transfer. USTAT contains the transfer
endpoint number, direction and Ping-Pong Buffer
Pointer value (if used).
The USTAT register is actually a read window into a
4-byte status FIFO, maintained by the SIE. It allows the
microcontroller to process one transfer while the SIE
processes additional endpoints (
4-byte status FIFO, maintained by the SIE. It allows the
microcontroller to process one transfer while the SIE
processes additional endpoints (
). When
the SIE completes using a buffer for reading or writing
data, it updates the USTAT register. If another USB
transfer is performed before a transaction complete
interrupt is serviced, the SIE will store the status of the
next transfer into the status FIFO.
data, it updates the USTAT register. If another USB
transfer is performed before a transaction complete
interrupt is serviced, the SIE will store the status of the
next transfer into the status FIFO.
Clearing the Transfer Complete Flag bit, TRNIF,
causes the SIE to advance the FIFO. If the next data in
the FIFO holding register is valid, the SIE will reassert
the interrupt within 5 T
causes the SIE to advance the FIFO. If the next data in
the FIFO holding register is valid, the SIE will reassert
the interrupt within 5 T
CY
of clearing TRNIF. If no addi-
tional data is present, TRNIF will remain clear; USTAT
data will no longer be reliable.
data will no longer be reliable.
FIGURE 27-3:
USTAT FIFO
Note:
The data in the USB Status register is
valid only when the TRNIF interrupt flag is
asserted.
valid only when the TRNIF interrupt flag is
asserted.
Note:
If an endpoint request is received while
the USTAT FIFO is full, the SIE will
automatically issue a NAK back to the host.
the USTAT FIFO is full, the SIE will
automatically issue a NAK back to the host.
Data Bus
USTAT from SIE
4-Byte FIFO
for USTAT
Clearing TRNIF
Advances FIFO
Advances FIFO
REGISTER 27-3:
USTAT: USB STATUS REGISTER (ACCESS F64H)
U-0
R-x
R-x
R-x
R-x
R-x
R-x
U-0
—
ENDP3
ENDP2
ENDP1
ENDP0
DIR
PPBI
(
)
—
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-3
ENDP<3:0>: Encoded Number of Last Endpoint Activity bits
(represents the number of the BDT updated by the last USB transfer)
1111 = Endpoint 15
1110 = Endpoint 14
.
.
.
0001 = Endpoint 1
0000 = Endpoint 0
(represents the number of the BDT updated by the last USB transfer)
1111 = Endpoint 15
1110 = Endpoint 14
.
.
.
0001 = Endpoint 1
0000 = Endpoint 0
bit 2
DIR: Last BD Direction Indicator bit
1 = The last transaction was an IN token
0 = The last transaction was an OUT or SETUP token
1 = The last transaction was an IN token
0 = The last transaction was an OUT or SETUP token
bit 1
PPBI: Ping-Pong BD Pointer Indicator bit
)
1 = The last transaction was to the Odd BD bank
0 = The last transaction was to the Even BD bank
0 = The last transaction was to the Even BD bank
bit 0
Unimplemented: Read as ‘0’
Note 1:
This bit is only valid for endpoints with available Even and Odd BD registers.