Microchip Technology DM183037 Data Sheet
PIC18F97J94 FAMILY
DS30575A-page 540
2012 Microchip Technology Inc.
27.5
USB Interrupts
The USB module can generate multiple interrupt condi-
tions. To accommodate all of these interrupt sources,
the module is provided with its own interrupt logic struc-
ture, similar to that of the microcontroller. USB interrupts
are enabled with one set of control registers and
trapped with a separate set of flag registers. All sources
are funneled into a single USB Oscillator Fail Interrupt
Flag bit, USBIF (PIR2<4>), in the microcontroller’s
interrupt logic.
tions. To accommodate all of these interrupt sources,
the module is provided with its own interrupt logic struc-
ture, similar to that of the microcontroller. USB interrupts
are enabled with one set of control registers and
trapped with a separate set of flag registers. All sources
are funneled into a single USB Oscillator Fail Interrupt
Flag bit, USBIF (PIR2<4>), in the microcontroller’s
interrupt logic.
module. There are two layers of interrupt registers in
the USB module. The top level consists of overall USB
status interrupts; these are enabled and flagged in the
UIE and UIR registers, respectively. The second level
consists of USB error conditions, which are enabled
and flagged in the UEIR and UEIE registers. An
interrupt condition in any of these triggers a USB Error
Interrupt Flag (UERRIF) in the top level.
Interrupts may be used to trap routine events in a USB
transaction.
the USB module. The top level consists of overall USB
status interrupts; these are enabled and flagged in the
UIE and UIR registers, respectively. The second level
consists of USB error conditions, which are enabled
and flagged in the UEIR and UEIE registers. An
interrupt condition in any of these triggers a USB Error
Interrupt Flag (UERRIF) in the top level.
Interrupts may be used to trap routine events in a USB
transaction.
provides some common
events within a USB frame and its corresponding
interrupts.
interrupts.
FIGURE 27-7:
USB INTERRUPT LOGIC FUNNEL
FIGURE 27-8:
EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS
BTSEF
BTSEE
BTOEF
BTOEE
DFN8EF
DFN8EE
CRC16EF
CRC16EE
CRC5EF
CRC5EE
PIDEF
PIDEE
SOFIF
SOFIE
TRNIF
TRNIE
IDLEIF
IDLEIE
STALLIF
STALLIE
ACTVIF
ACTVIE
URSTIF
URSTIE
UERRIF
UERRIE
USBIF
Second Level USB Interrupts
(USB Error Conditions
UEIR (Flag) and UEIE (Enable) Registers
Top Level USB Interrupts
(USB Status Interrupts
UIR (Flag) and UIE (Enable) Registers
USB Reset
SOF
RESET
SETUP
DATA
STATUS
SOF
SETUPToken
Data
ACK
OUT Token
Empty Data
ACK
Start-of-Frame (SOF)
IN Token
Data
ACK
SOFIF
URSTIF
1 ms Frame
Differential Data
From Host
From Host
To Host
From Host
To Host
From Host
From Host
From Host
To Host
Transaction
Control Transfer
(1)
Transaction
Complete
Note 1:
The control transfer shown here is only an example showing events that can occur for every transaction. Typical
control transfers will spread across multiple frames.
control transfers will spread across multiple frames.
Set TRNIF
Set TRNIF
Set TRNIF