Microchip Technology DM183037 Data Sheet
PIC18F97J94 FAMILY
DS30575A-page 568
2012 Microchip Technology Inc.
28.2
Watchdog Timer (WDT)
For the PIC18F97J94 family of devices, the WDT is
driven by the LF-INTOSC source. When the WDT is
enabled, the clock source is also enabled. The nominal
WDT period is 4 ms and has the same stability as the
LF-INTOSC Oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in
Configuration Register 2H. Available periods range
from 4 ms to 4,194 seconds (about one hour). The
WDT and postscaler are cleared when any of the
following events occur: a SLEEP or CLRWDT instruction
is executed, the IRCFx bits (OSCCON3<2:0>) are
changed or a clock failure has occurred.
driven by the LF-INTOSC source. When the WDT is
enabled, the clock source is also enabled. The nominal
WDT period is 4 ms and has the same stability as the
LF-INTOSC Oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in
Configuration Register 2H. Available periods range
from 4 ms to 4,194 seconds (about one hour). The
WDT and postscaler are cleared when any of the
following events occur: a SLEEP or CLRWDT instruction
is executed, the IRCFx bits (OSCCON3<2:0>) are
changed or a clock failure has occurred.
28.2.1
WINDOWED OPERATION
The Watchdog Timer has an optional Fixed Window
mode of operation. In this Windowed mode, CLRWDT
instructions can only reset the WDT during the last 1/4
of the programmed WDT period. A CLRWDT instruction
executed before that window causes a WDT Reset,
similar to a WDT time-out.
mode of operation. In this Windowed mode, CLRWDT
instructions can only reset the WDT during the last 1/4
of the programmed WDT period. A CLRWDT instruction
executed before that window causes a WDT Reset,
similar to a WDT time-out.
Windowed WDT mode is enabled by programming the
WINDIS Configuration bit (CONFIG6H<2>) to ‘0’.
The WDT can be operated in one of four modes, as
determined by WDTEN<1:0> (CONFIG6H<1:0>. The
four modes are:
• WDT Enabled
• WDT Disabled
• WDT under Software Control,
WINDIS Configuration bit (CONFIG6H<2>) to ‘0’.
The WDT can be operated in one of four modes, as
determined by WDTEN<1:0> (CONFIG6H<1:0>. The
four modes are:
• WDT Enabled
• WDT Disabled
• WDT under Software Control,
SWDTEN (RCON2<5>)
• WDT:
- Enabled during normal operation
- Disabled during Sleep
- Disabled during Sleep
FIGURE 28-1:
WDT BLOCK DIAGRAM
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
when executed.
2: Changing the setting of the IRCFx bits
(OSCCON3<2:0>) clear the WDT and
postscaler counts.
postscaler counts.
3: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
INTOSC Source
WDT
Reset
WDT Counter
Enable WDT
WDTPS<3:0>
CLRWDT
4
Reset
All Device Resets
Sleep
128
Change on IRCFx bits
INTOSC Source
Enable WDT
SWDTEN
WDTEN<1:0>
WDTEN1
WDTEN0
WDTEN0
WDT Enabled,
SWDTEN Disabled
WDT Controlled with
SWDTEN bit Setting
WDT Enabled only while
Device Active, Disabled
WDT Disabled in Hardware,
SWDTEN Disabled
Wake-up from
Power-Managed
Modes
Power-Managed
Modes
Programmable Postscaler
1:1 to 1:1,048,576