Microchip Technology DM183037 Data Sheet
PIC18F97J94 FAMILY
DS30575A-page 570
2012 Microchip Technology Inc.
28.3
Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the
latency period from oscillator start-up to code execution
by allowing the microcontroller to use the INTOSC
(LF-INTOSC, MF-INTOSC, HF-INTOSC) Oscillator as a
clock source until the primary clock source is available.
It is enabled by setting the IESO Configuration bit.
Two-Speed Start-up should be enabled only if the Pri-
mary Oscillator mode is LP, MS or HS (Crystal-Based
modes). Other sources do not require an OST start-up
delay; for these, Two-Speed Start-up should be
disabled.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the
internal oscillator block as the clock source, following the
time-out of the Power-up Timer (PWRT) after a Power-
on Reset is enabled. This allows almost immediate code
execution while the Primary Oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
To use a higher clock speed on wake-up, the INTOSC or
postscaler clock sources can be selected to provide a
higher clock speed by setting bits, IRCF<2:0>,
immediately after Reset. For wake-ups from Sleep, the
INTOSC or postscaler clock sources can be selected by
setting the IRCF2:0> bits prior to entering Sleep mode.
latency period from oscillator start-up to code execution
by allowing the microcontroller to use the INTOSC
(LF-INTOSC, MF-INTOSC, HF-INTOSC) Oscillator as a
clock source until the primary clock source is available.
It is enabled by setting the IESO Configuration bit.
Two-Speed Start-up should be enabled only if the Pri-
mary Oscillator mode is LP, MS or HS (Crystal-Based
modes). Other sources do not require an OST start-up
delay; for these, Two-Speed Start-up should be
disabled.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the
internal oscillator block as the clock source, following the
time-out of the Power-up Timer (PWRT) after a Power-
on Reset is enabled. This allows almost immediate code
execution while the Primary Oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
To use a higher clock speed on wake-up, the INTOSC or
postscaler clock sources can be selected to provide a
higher clock speed by setting bits, IRCF<2:0>,
immediately after Reset. For wake-ups from Sleep, the
INTOSC or postscaler clock sources can be selected by
setting the IRCF2:0> bits prior to entering Sleep mode.
In all other power-managed modes, Two-Speed Start-up
is not used. The device will be clocked by the cur-
rently selected clock source until the primary clock
source becomes available. The setting of the IESO
Configuration bit is ignored.
is not used. The device will be clocked by the cur-
rently selected clock source until the primary clock
source becomes available. The setting of the IESO
Configuration bit is ignored.
28.3.1
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
USING TWO-SPEED START-UP
While using the INTOSC Oscillator in Two-Speed Start-
up, the device still obeys the normal command
sequences for entering power-managed modes,
including multiple SLEEP instructions. In practice, this
up, the device still obeys the normal command
sequences for entering power-managed modes,
including multiple SLEEP instructions. In practice, this
means that user code can change the NOSC<2:0> bit
settings or issue SLEEP instructions before the OST
settings or issue SLEEP instructions before the OST
times out. This would allow an application to briefly
wake-up, perform routine “housekeeping” tasks and
return to Sleep before the device starts to operate from
the Primary Oscillator.
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the COSC<2:0> bits (OSCCON<2:0>). If the
bit is set, the Primary Oscillator is providing the clock.
Otherwise, the internal oscillator block is providing the
clock during wake-up from Reset or Sleep mode.
wake-up, perform routine “housekeeping” tasks and
return to Sleep before the device starts to operate from
the Primary Oscillator.
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the COSC<2:0> bits (OSCCON<2:0>). If the
bit is set, the Primary Oscillator is providing the clock.
Otherwise, the internal oscillator block is providing the
clock during wake-up from Reset or Sleep mode.
FIGURE 28-2:
TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)
Q1
Q3 Q4
OSC1
Peripheral
Program
PC
PC + 2
INTOSC
PLL Clock
Q1
PC + 6
Q2
Output
Q3
Q4
Q1
CPU Clock
PC + 4
Clock
Counter
Q2
Q2
Q3
Note 1: T
OST
= 1024 T
OSC
; T
PLL
= 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 T
OSC
.
Wake from Interrupt Event
T
PLL(1)
1
2
n-1 n
Clock
OST Expired
Transition
(2)
Multiplexer
T
OST(1)