Microchip Technology DM183037 Data Sheet
2012 Microchip Technology Inc.
DS30575A-page 645
PIC18F97J94 FAMILY
FIGURE 31-5:
PROGRAM MEMORY FETCH TIMING DIAGRAM (8-BIT)
TABLE 31-20: PROGRAM MEMORY FETCH TIMING REQUIREMENTS (8-BIT)
Param
No
Symbol
Characteristics
Min
Typ Max
Units
150
TadV2aIL
Address Out Valid to ALE
(address setup time)
0.25 T
CY
– 10
—
—
ns
151
TaIL2adl
ALE
to Address Out Invalid (address hold time)
5
—
—
ns
153
B
A
01
BA0
to Most Significant Data Valid
0.125 T
CY
—
—
ns
154
B
A
02
BA0
to Least Significant Data Valid
0.125 T
CY
—
—
ns
155
TaIL2oeL
ALE
to OE
0.125 T
CY
—
—
ns
161
ToeH2adD OE
to A/D Driven
0.125 T
CY
– 5
—
—
ns
162
TadV2oeH Least Significant Data Valid Before OE
(data setup time)
20
—
—
ns
162A
TadV2oeH Most Significant Data Valid Before OE
(data setup time)
0.25 T
CY
+ 20
—
—
ns
163
ToeH2adI OE
to Data in Invalid (data hold time)
0
—
—
ns
166
TaIH2aIH
ALE
to ALE (cycle time)
—
T
CY
—
ns
167
T
ACC
Address Valid to Data Valid
0.5 T
CY
– 10
—
—
ns
168
Toe
OE
to Data Valid
—
—
0.125 T
CY
+ 5
ns
170
TubH2oeH BA0 = 0 Valid Before OE
0.25 T
CY
—
—
ns
170A
TubL2oeH BA0 = 1 Valid Before OE
0.5 T
CY
—
—
ns
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
ALE
OE
Address
Data
170
161
162
AD<7:0>
Address
Address
A<19:8>
Address
162A
BA0
Data
170A
151
150
166
167
155
153
163
154
168
CE
Note: Fmax = 25 MHz in 8-Bit External Memory mode.