Microchip Technology DM183037 Data Sheet
2012 Microchip Technology Inc.
DS30575A-page 73
PIC18F97J94 FAMILY
4.4.10
CONTROL BIT SUMMARY FOR
SLEEP MODES
SLEEP MODES
shows the settings for the bits relevant to
Deep Sleep modes.
TABLE 4-5:
BIT SETTINGS FOR ALL DEEP SLEEP MODES
4.4.11
WAKE-UP DELAYS
The Reset delays associated with wake-up from Deep
Sleep and Retention Deep Sleep modes, in different
oscillator modes, are provided in
Sleep and Retention Deep Sleep modes, in different
oscillator modes, are provided in
and
, respectively.
TABLE 4-6:
DELAY TIMES FOR EXITING FROM DEEP SLEEP MODE
Instruction-Based
Mode
DSEN
(DSCONH<7>)
Retention Regulator
DSWDTEN
(CONFIG8H<0>)
RETEN
(CONFIG7L<0>)
SRETEN
(RCON4<4>)
State
Retention Deep Sleep
1
0
1
Enabled
0
Deep Sleep
1
1
x
Disabled
x
Note:
The PMSLP bit (RCON4<0>) allows the
voltage regulator to be maintained during
Sleep modes.
voltage regulator to be maintained during
Sleep modes.
Clock Source
Exit Delay
Oscillator Delay
Notes
EC
T
DSWU
—
ECPLL
T
DSWU
T
LOCK
MS, HS
T
DSWU
T
OST
MSPLL, HSPLL
T
DSWU
T
OST
+ T
LOCK
SOSC
(Off during Sleep)
T
DSWU
T
OST
(On during Sleep)
T
DSWU
—
FRC, FRCDIV
T
DSWU
T
FRC
LPRC
(Off during Sleep)
T
DSWU
T
LPRC
(On during Sleep)
T
DSWU
—
FRCPLL
T
DSWU
T
FRC
+ T
LOCK
Note 1: T
DSWU
= Deep Sleep wake-up delay.
2: T
OST
= Oscillator Start-up Timer; a delay of 1024 oscillator periods before the oscillator clock is released to
the system.
3: T
LOCK
= PLL lock time.
4: T
FRC
and T
LPRC
are RC Oscillator start-up times.