Microchip Technology DM183037 Data Sheet

 2012 Microchip Technology Inc.

DS30575A-page 85

The PIC18F97J94 family devices differentiate between
various kinds of Reset: 
a)

Power-on Reset (POR) 

b)

MCLR Reset

c)

Watchdog Timer (WDT) Reset

d)

Configuration Mismatch (CM)

e)

Brown-out Reset (BOR) 

f)

RESET Instruction

g)

Stack Underflow/Overflow Reset

This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers. For information on WDT Resets, see

. For Stack

Reset events, see 

. For Deep Sleep mode, see

.

A simplified block diagram of the On-Chip Reset Circuit
is shown in 

Device Reset events are tracked through the RCON,
RCON2, RCON3 and RCON4 registers (

, 

). The regis-

ter bits indicate that a specific Reset event has occurred.
Depending on the definition, status bits may be set or
cleared by the event, and re-initialized by the applica-
tion, after the event to the opposite state. Setting or
clearing Reset status bits does not cause a Reset.
The state of these flag bits, taken together, can be read
to indicate the type of Reset that just occurred.
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in 

.

External Reset

MCLR

V

DD

OSC1

V

DD

 Rise

Detect

OST/PWRT

INTOSC

POR Pulse

OST

10-Bit Ripple Counter

PWRT

Internal Reset

11-Bit Ripple Counter

Enable OST

Enable PWRT

Note 1: This is the INTOSC source from the internal oscillator block and is separate from the RC Oscillator of the CLKI pin.

2: See 

 for time-out situations.

Brown-out

Reset

BOREN

RESET

Instruction

Stack

Pointer

Stack Full/Underflow Reset

Sleep

Idle

1024 Cycles

1 ms

32 

s

MCLRE

WDT

Time-out

S

R

Q