Freescale Semiconductor Xtrinsic MMA955xL Intelligent Motion-Sensing Platform KITMMA9550LEVM KITMMA9550LEVM User Manual

Freescale Semiconductor, Inc.

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2

SC

STOP Mode Enable for STOP With Slow Clock
The FC, SC and NC bits are mutually exclusive. They control the mode of operation to be initiated 
by the next STOP instruction. A maximum of one of the three can be asserted at any time. If none 
of them are enabled, STOP is considered an illegal instruction. Instead of entering one of the STOP 
modes, the MCU will initiate an illegal opcode reset if CPUCR[IRD] is cleared. If CPUCR[IRD] is set, 
an illegal instruction exception is initiated. (For details, 

.)

If the CPU attempts to write more than one of FC, SC or NC, all three will be cleared and, again, 
STOP will be considered an illegal instruction.
0 STOP with Slow Clock is NOT enabled.
1 The next STOP instruction will result in the CPU entering STOP, with the oscillator in low-speed 

mode.

1

NC

STOP Mode Enable for STOP With No Clock
The FC, SC and NC bits are mutually exclusive. They control the mode of operation to be initiated 
by the next STOP instruction. A maximum of one of the three can be asserted at any time. If none 
of them are enabled, STOP is considered an illegal instruction. Instead of entering one of the STOP 
modes, the MCU will initiate an illegal opcode reset if CPUCR[IRD] is cleared. If CPUCR[IRD] is set, 
an illegal instruction exception is initiated. (For details, 

.)

If the CPU attempts to write more than one of FC, SC or NC, all three will be cleared and, again, 
STOP will be considered an illegal instruction.
0 STOP with No Clock is NOT enabled.
1 The next STOP instruction will result in the CPU entering STOP, with the oscillator disabled. The 

device will be in deep-sleep mode. In this mode, the device can be awakened only by 
asynchronous interrupts (one of which can be initiated via the slave I

2

C interface) or a reset 

assertion.

0

SCtoFC

Slow Clock to Fast Clock STOP Transition Enabled
The device can be programmed to transition from STOP

SC

 to STOP

FC

 when a “Start Sample Frame” 

signal is asserted. Simply program SCtoFC to 1. This bit allows the CPU to initiate IDLE mode with 
a STOP

SC

 transition. That state will automatically transition to STOP

FC

 when the AFE needs to be 

started up for the next frame. This operation occurs without CPU intervention if this bit is set.
0 Automatic transition from STOP

SC

 to STOP

FC

 is not enabled.

1 The “Start Sample Frame” signal will cause the device to transition from STOP

SC

 to STOP

FC

 

should it occur while the device is parked in STOP

SC

. It has no affect otherwise.