Freescale Semiconductor Evaluation Kit (EVK) for the i.MX51 Applications Processor MCIMX51EXP MCIMX51EXP Data Sheet
Product codes
MCIMX51EXP
Electrical Characteristics
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
Freescale Semiconductor
67
shows the timing diagram for mDDR SDRAM write cycle. The timing parameters for this
diagram is shown in
Figure 33. mDDR SDRAM Write cycle Timing Diagram
Table 56. mDDR SDRAM Write Cycle Parameter Table
1
1
Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for
address and controls.
address and controls.
ID
Parameter
Symbol
200 MHz
2
2
SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal
value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK
and SDCLK (inverted clock).
value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK
and SDCLK (inverted clock).
166 MHz
133 MHz
Unit
Min
Max
Min
Max
Min
Max
DD17
DQ and DQM setup time to DQS
t
DS
3
3
This parameter is affected by pad timing. If the slew rate is < 1 V/ns, 0.1 ns should be increased to this value.
0.48
—
0.6
—
0.8
—
ns
DD18
DQ and DQM hold time to DQS
t
DH
1
0.48
—
0.6
—
0.8
—
ns
DD19
Write cycle DQS falling edge to
SDCLK output setup time
SDCLK output setup time
t
DSS
0.2
—
0.2
—
0.2
—
tCK
DD20
Write cycle DQS falling edge to
SDCLK output hold time
SDCLK output hold time
t
DSH
0.2
—
0.2
—
0.2
—
tCK
DD21
Write command to first DQS latching
transition
transition
t
DQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DD22
DQS high level width
t
DQSH
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DD23
DQS low level width
t
DQSL
0.4
0.6
0.4
0.6
0.4
0.6
tCK
SDCLK
SDCLK_B
DQS (output)
DQ (output)
DQM (output)
Data
Data
Data
Data
Data
Data
Data
Data
DM
DM
DM
DM
DM
DM
DM
DM
DD17
DD17
DD17
DD17
DD18
DD18
DD18
DD18
DD19
DD20
DD21
DD23
DD22