Freescale Semiconductor Evaluation Kit (EVK) for the i.MX51 Applications Processor MCIMX51EXP MCIMX51EXP Data Sheet
Product codes
MCIMX51EXP
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
68
Freescale Semiconductor
Electrical Characteristics
shows the timing diagram for mDDR SDRAM DQ versus DQS and SDCLK read
cycle. The
timing parameters for this diagram is shown in
Figure 34. mDDR SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram
Table 57. mDDR SDRAM Read Cycle Parameter Table
1
1
Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for
address and controls
address and controls
ID
PARAMETER
Symbol
200 MHz
2
2
SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal
value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK
and SDCLK (inverted clock)
value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK
and SDCLK (inverted clock)
166 MHz
133 MHz
Unit
Min Max Min Max Min Max
DD24 DQS - DQ Skew (defines the Data valid window in read cycles
related to DQS)
t
DQSQ
—
0.4
—
0.75
—
0.85
ns
DD25 DQS DQ in HOLD time from DQS
t
QH
1.75
—
2.05
—
2.6
—
ns
DD26 DQS output access time from SDCLK posedge
t
DQSCK
2
5
2
5.5
2
6.5
ns
SDCLK
SDCLK_B
DQS (input)
DQ (input)
Data
Data
Data
Data
Data
Data
Data
Data
DD26
DD24
DD25