Freescale Semiconductor Evaluation Kit (EVK) for the i.MX51 Applications Processor MCIMX51EXP MCIMX51EXP Data Sheet
Product codes
MCIMX51EXP
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
70
Freescale Semiconductor
Electrical Characteristics
NOTE
Measurements are taken from Vref to Vref (cross-point to cross-point), but
JEDEC timings for single-ended signals are defined from Vref to Vil(ac)
max or to Vih(ac) min.
JEDEC timings for single-ended signals are defined from Vref to Vil(ac)
max or to Vih(ac) min.
DDR6
Address output setup time
t
IS
1.7
—
ns
DDR7
Address output hold time
t
1.5
—
ns
1
These values are for command/address slew rates of 1 V/ns and SDCLK / SDCLK_B differential slew rate of 2 V/ns. For
different values use the settings shown in
different values use the settings shown in
Table 59.
Derating Values for DDR2-400 (SDCLK = 200 MHz)
Command /
Address
Slew Rate
(V/ns)
SDCLK Differential Slew Rates
1,2
Unit
2.0 V/ns
1.5 V/ns
1.0 V/ns
Δ
tlS
Δ
tlH
Δ
tlS
Δ
tlH
Δ
tlS
Δ
tlH
4.0
+187
+94
+217
+124
+247
+154
ps
3.5
+179
+89
+209
+119
+239
+149
ps
3.0
+167
+83
+197
+113
+227
+143
ps
2.5
+150
+75
+180
+105
+210
+135
ps
2.0
+125
+45
+155
+75
+185
+105
ps
1.5
+83
+21
+113
+51
+143
+81
ps
1.0
+0
+0
+30
+30
+60
+60
ps
0.9
–11
–14
+19
+16
+49
+46
ps
0.8
–25
–31
+5
–1
+35
+29
ps
0.7
–43
–54
–13
–24
+17
+6
ps
0.6
–67
–83
–37
–53
–7
–23
ps
0.5
–110
–125
–80
–95
–50
–65
ps
0.4
–175
–188
–145
–158
–115
–128
ps
0.3
–285
–292
–255
–262
–225
–232
ps
0.25
–350
–375
–320
–345
–290
–315
ps
0.2
–525
–500
–495
–470
–465
–440
ps
0.15
–800
–708
–770
–678
–740
–648
ps
0.1
–1450
–1125
–1420
–1095
–1390
–1065
ps
Table 58. DDR2 SDRAM Timing Parameter Table (continued)
ID
Parameter
Symbol
SDCLK = 200 MHz
Unit
Min
Max