AMD Phenom 8450 Triple-Core HD8450WCGHBOX User Manual
Product codes
HD8450WCGHBOX
12
MSRC001_0140 OS Visible Work-around MSR0 (OSVW_ID_Length)
41322
Rev. 3.16 February 2008
Revision Guide for AMD Family 10h Processors
MSRC001_0140 OS Visible Work-around MSR0
(OSVW_ID_Length)
(OSVW_ID_Length)
This register, as defined in AMD64 Architecture Programmer’s Manual Volume 2: System
Programming, order# 24593, is used to specify the number valid status bits within the OS Visible
Work-around status registers.
Programming, order# 24593, is used to specify the number valid status bits within the OS Visible
Work-around status registers.
The default value of this register is 0000_0000_0000_0000h.
BIOS shall program the specified length as specified in Table 8 prior to hand-off to the OS.
Bits
Description
63:16
Reserved.
15:0
OSVW_ID_Length: OS visible work-around ID length. Read-write
Table 8.
OSVW_ID_Length Per Processor Revision
MSRC001_1040
Bits
Revision Number
DR-BA
DR-B2
15:0
0001h
0001h