AMD Phenom 8450 Triple-Core HD8450WCGHBOX User Manual

41322

Rev. 3.16

February 2008

This register, as defined in AMD64 Architecture Programmer’s Manual Volume 2: System 
Programming, order# 24593, provides the status of the known OS visible errata. Known errata are 
assigned an OSVW_ID corresponding to the bit position with in the valid status field.

Operating system software should use MSRC001_0140 to determine the valid length of the bit status 
field. For all valid status bits: 1=Hardware contains the erratum, and an OS software work-around is 
required or may be applied instead of a BIOS workaround. 0=Hardware has corrected the erratum, so 
an OS software work-around is not necessary.

The reset default value of this register is 0000_0000_0000_0000h.

BIOS shall program the state of the valid status bits prior to hand-off to the OS as defined in the 
description below.

63:1

OsvwStatusBits: OS visible work-around status bits. Read-write.

0

OsvwId0: OsvwId0 1= Hardware contains erratum #298, an OS workaround may be applied if 
available. 0= Hardware has corrected erratum #298. In a multiprocessor platform, OsvwId0 
should be set to 1 for all processors regardless of silicon revision when an affected processor is 
present. Read-write.